ICS662M-03LFT IDT, Integrated Device Technology Inc, ICS662M-03LFT Datasheet - Page 3

• Manufacturer Part Number: ICS662M-03LFT
• Description: IC CLK SOURCE HDTV AUD/VID 8SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of ICS662M-03LFT

• Applications: HDTV, MPEG, Image Processing
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 662M-03LFT

Application Information
Series Termination Resistor
Clock output traces should use series termination. To series
terminate a 50 trace (a commonly used trace impedance),
place a 33 resistor in series with the clock line, as close to
the clock output pin as possible. The nominal impedance of
the clock output is 20 .
Decoupling Capacitors
As with any high performance mixed-signal IC, the
ICS662-03 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between VDD (pin 2) and the PCB ground plane (pin 3).
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) Each 0.01µF decoupling capacitor should be mounted on
Absolute Maximum Ratings
Recommended Operation Conditions
IDT™ / ICS™ HDTV AUDIO/VIDEO CLOCK SOURCE
ICS662-03
HDTV AUDIO/VIDEO CLOCK SOURCE
Stresses above the ratings listed below can cause permanent damage to the ICS662-03. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Item
3
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) To minimize EMI and obtain the best signal integrity, the
33 series termination resistor should be placed close to
the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the ICS662-03. This includes signal traces just
underneath the device, or on layers adjacent to the ground
plane layer used by the device.
Min.
+3.0
0
5.5 V
-0.5 V to VDD+0.5 V
0 to +70 C
-65 to +150 C
125 C
260 C
Typ.
Rating
Max.
+3.6
+70
CLOCK SYNTHESIZER
ICS662-03
Units
V
C
REV G 051310