TDA9984AHW/15/C181 NXP Semiconductors, TDA9984AHW/15/C181 Datasheet - Page 27

• Manufacturer Part Number: TDA9984AHW/15/C181
• Description: HDMI TRANSMITTER 1080P 80HTQFP
• Manufacturer: NXP Semiconductors
• Type: HDMI 1.3 Transmitterr

Specifications of TDA9984AHW/15/C181

• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Applications: Set-Top Boxes, Video Players, Recorders
• Mounting Type: Surface Mount
• Operating Supply Voltage: 1.8 V, 3.3 V
• Supply Current: 6 mA to 283 mA
• Bandwidth: 150 MHz
• Conversion Rate: 12 bit
• Maximum Power Dissipation: 1080 mW
• Mounting Style: SMD/SMT
• Resolution: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935288944518

NXP Semiconductors
TDA9984A_4
Product data sheet
8.6.2.1 E-EDID reading
8.6.2.2 HDMI and DVI receiver discrimination
8.5.5 Power management
8.6.1 DDC-bus channel
8.6.2 E-EDID
8.6 DDC-bus interface
The TDA9984A can be powered down via the I
switched off and the biasing structure of the output stage is disconnected (all activity is
reduced). Therefore, the TDA9984A has a very low power consumption which is suitable
for portable applications.
The DDC-bus pins DDC_SDA and DDC_SCL are 5 V tolerant and can work at
Standard-mode (100 kHz) and Fast-mode (400 kHz). The DDC-bus is used as a master
interface in case of EDID reading, and while proceeding for HDCP. It is recommended not
going beyond 100 kHz for EDID as claimed by the HDMI specification. This frequency is
linked to the internal free running oscillator whose nominal frequency is 30 MHz as:
Where:
Then for convenience, it is recommended to keep the same frequency for HDCP purpose.
As a master interface for the EDID process, the DDC-bus is compliant to the I
specification and has the possibility of the repeat and start condition to enable quick
access to the EDID content, as well as the large EDID reading possibility (with the use of
a segment pointer).
The TDA9984A has a full I
block can be stored. The block can be read by the microprocessor to determine the
supported video and audio format of the downstream side.
Remark: When the block is read by the TDA9984A, it generates an interrupt to warn the
main processor that the TDA9984A is ready to transmit the content. Once the content is
read-out by the microprocessor, it can allow reading other blocks if required.
This information is located in the E-EDID receiver part, more exactly in the ‘Vendor
Specific Data block within the first CEA EDID timing extension.
If the 24-bit IEEE Registration Identifier contains the value 00 0C03h, then the receiver will
support HDMI; otherwise the device shall be treated as a DVI device.
However, even though the TDA9984A have directly access to that information, this is the
task of the microcontroller to ask to switch from DVI to HDMI mode.
f
DDC
f
N
FRO
clk-div
=
= free running oscillator frequency
--------------------------------- -
3 2N
= value set by register
f
FRO
clk div
–
Rev. 04 — 15 January 2009
2
C-bus page (page 09h) dedicated to the EDID where one
HDMI 1.3 transmitter with 1080p upscaler embedded
2
C-bus register. In this mode, all PLLs are
TDA9984A
© NXP B.V. 2009. All rights reserved.
2
C-bus
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