MAX9134GHJ+ Maxim Integrated Products, MAX9134GHJ+ Datasheet - Page 13

• Manufacturer Part Number: MAX9134GHJ+
• Description: IC SW LVDS CROSSBAR 32TQFP-EP
• Manufacturer: Maxim Integrated Products
• Type: LVDS Crossbar Switchr

Specifications of MAX9134GHJ+

• Applications: Digital Video
• Mounting Type: Surface Mount
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

face. The routing action takes place after correct check-
sum verification. The LIN status register (0x00) holds the
error flags for the LIN transceiver. For a write, the master
writes 2 bytes of data to the registers (0x01, 0x02). For a
read, the slave outputs the contents of registers 0x00,
0x01, and 0x02, along with the stuffing byte at a constant
value (0xFF). In either mode, the checksum follows at the
end of the data bytes. Figure 3 shows the write and read
signal frame format. Figure 4 shows the LIN write and
read data frame.
The LIN bus uses the 8-bit protected identifier (PID) to
address the slave nodes. Two parity bits (MSBs) along
with 6 ID bits (LSBs) make up the PID field. Table 4
defines the sets of the identifiers for the write/read
operations of the LIN slave node. AS0 selects the iden-
tifiers. AS1/NSLP becomes the NSLP output for activat-
ing the LIN driver chip (MAX13020).
Register 0x00 contains the error flags found in the LIN
signal by the slave note (Table 5). A successful LIN
read resets register 0x00.
For the MAX9134/MAX9135, the routing can be con-
trolled by the hardware pins (S[5:0]). If the I
0xFF is not written by 0xFF, then chip routing is deter-
mined by S[5:0]. Also, these pins set the initial power-
up routing condition of the chip. Table 6a gives the
details of the routing control for the MAX9134. Table 6b
gives the details of the routing control for the MAX9135.
Once the I
Table 5. Register 0x00 Error Flag Mapping for LIN
Table 4. LIN Identifiers for Write and Read Operations
Pin Control by S[5:0] (MAX9134/MAX9135)
REGISTER BIT(S)
Open
High
AS0
Low
D[7:5]
D4
D3
D2
D1
D0
2
C register 0xFF is written by 0xFF, the I
______________________________________________________________________________________
ID[5:0]
0x1C
0x0A
0x08
Input/Output LVDS Crossbar Switches
DESCRIPTION
Checksum
Reserved
Programmable, High-Speed, Multiple
Transmit
Frame
Parity
Sync
LIN-Protected Identifier
WRITE ID
LIN Error Handling
Reserved
Sync pulse widths outside the given tolerances detected
Value read on RXD different from value transmitted on TXD during a read
Checksum sent during a write does not match the expected checksum
ID parity bit does not match expected parity
Message frame did not complete within the maximum allowed time
2
C register
PID FIELD
0xCA
0x9C
0x08
2
C
Figure 5. Connecting the MAX9132/MAX9134/MAX9135 to the
MAX13020
registers 0x01 and 0x02 take over the routing and the
pin (S[5:0]) setting is ignored. After the I
takes place, the pin setting can be changed without
affecting the routing. The new pin setting takes effect if
the PD pin or the chip supply is toggled. Usually, once
I
pin routing.
The MAX9132/MAX9134/MAX9135 use several 3-level
inputs to control the device. Use three-state logic to
realize the 3-level logic using digital control.
Alternatively, if a high-impedance output is unavailable,
apply a voltage of V
impedance state.
2
C controls the routing, there is no value in using the
MAX9132
MAX9134
MAX9135
V
DD
FUNCTION
ID[5:0]
0x27
0x29
0x2B
Applications Information
TXD
RXD
NSLP
DD
5kΩ
/2 to realize the midlevel high-
READ ID
5kΩ
INH
TXD
RXD
NSLP
MAX13020
V
BAT
3-Level Inputs
NWAKE
PID FIELD
LIN
0xE7
0xE9
0x2B
2
C routing
5kΩ
LIN
BUS
13