MAX7370 Maxim, MAX7370 Datasheet - Page 16

• Manufacturer Part Number: MAX7370
• Description: The MAX7370 I²C-interfaced peripheral provides microprocessors with management of up to 64 key switches, with optional GPIO and PWM-controlled LED drivers
• Manufacturer: Maxim

with I
Figure 4. Acknowledge
Figure 5. Slave Address
Table 3. Two-Wire Interface Address Map
The device has two 7-bit long slave addresses. The bit
following a 7-bit slave address is the R/W bit, which is
low for a write command and high for a read command.
The first 4 bits (MSBs) of the device slave addresses
are always 0111. Slave address bits A[3:1] correspond,
by the matrix in
address input pin AD0, and A0 corresponds to the
R/W bit
to any of four signals: GND, V
ing four possible slave-address pairs, allowing up to
four devices to share the same bus. Because SDA and
SCL are dynamic signals, care must be taken to ensure
that AD0 transitions no sooner than the signals on
SDA and SCL.
The device monitors the bus continuously, waiting for a
START condition, followed by its slave address. When
the device recognizes its slave address, it acknowledges
and is then ready for continued communication.
GND
V
SDA
SCL
CC
AD0
PIN
8 x 8 Key-Switch Controller and LED Driver/GPIOs
(Figure
A7
0
2
C Interface and High Level of ESD Protection
A6
5). The AD0 input can be connected
TRANSMITTER
1
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Table
RECEIVER
SDA BY
SDA BY
SDA
SCL
A5
SCL
1
DEVICE ADDRESS
3, to the states of the device
CONDITION
MSB
START
A4
1
0
S
CC
A3
0
0
1
1
Slave Addresses
, SDA, or SCL, giv-
1
A2
0
1
0
1
1
A1
1
0
R/W
A0
1
2
A3
The device features a 20ms (min) bus timeout on the
two-wire serial interface, largely to prevent the device
from holding the SDA I/O low during a read transac-
tion should the SCL lock up for any reason before a
serial transaction is completed. Bus timeout operates by
causing the device to internally terminate a serial trans-
action, either read or write, if the time between adjacent
edges on SCL exceeds 20ms. After a bus timeout, the
device waits for a valid START condition before respond-
ing to a consecutive transmission. This feature can be
enabled or disabled under user control by writing to the
configuration register.
A write to the device comprises the transmission of the slave
address with the R/W bit set to zero, followed by at least one
byte of information. The first byte of information is the com-
mand byte. The command byte determines which register
of the device is to be written by the next byte, if received.
If a STOP condition is detected after the command byte
is received, the device takes no further action
beyond storing the command byte.
Any bytes received after the command byte are data bytes.
The first data byte goes into the internal register of the
device selected by the command byte
If multiple data bytes are transmitted before a STOP condi-
tion is detected, these bytes are generally stored in sub-
sequent internal registers of the device, because the com-
mand-byte address generally autoincrements
A2
LSB
A1
CLOCK PULSE FOR
8
ACKNOWLEDGE
R/W
Message Format for Writing
the Keyscan Controller
ACK
9
MAX7370
(Figure
Bus Timeout
(Table
7).
(Figure
4).
6)