DS8007A Maxim, DS8007A Datasheet - Page 38

• Manufacturer Part Number: DS8007A
• Description: The DS8007A multiprotocol dual smart card interface is an automotive grade, low-cost, dual smart card reader interface supporting all ISO 7816, EMV™, and GSM11-11 requirements
• Manufacturer: Maxim

The T = 1 protocol does not support error-signal gener-
ation. When configured to receive using the T = 0 pro-
tocol (UCR1.PROT = 0), the DS8007A supports error-
signal generation in response to parity. The parity error
count bits (PEC2–PEC0) of the FIFO control register
(FCR) determine the number of allowed repetitions in
reception, and therefore the number of times that an
error signal is generated in response to a received
character with incorrect parity before the USR.PE bit
becomes set.
When receiving a character, the DS8007A verifies
even parity for the combination of the received 8-bit
character and parity bit. If incorrect parity is deter-
mined and consecutive parity error counter has not
reached terminal count (000b), the DS8007A gener-
ates an error signal on the I/Ox line starting at 10.5
ETU and lasting for 1.0 ETU. The parity error counter is
initialized through the PEC2–PEC0 bits. Configuring
the PEC2–PEC0 bits to 000b means that no repetition
in reception is allowed and that an error signal genera-
tion occurs in response to a character received with
incorrect parity. Configuring PEC2–PEC0 bits to 001b
means one repetition in reception is allowed and that
the DS8007A generates an error signal only once per
character receive attempt. When the consecutive pari-
ty error counter reaches 000b and a character is
Multiprotocol Dual Smart Card Interface
Figure 16. Receive Mode—Error Signal Generation
38
ETU TIME =>
______________________________________________________________________________________
0
1
2
3
Error-Signal Generation
4
CHARACTER N
5
PARITY BIT DOES NOT CHECK
ERROR-SIGNAL GENERATION (T = 0 PROTOCOL ONLY)
6
7
8
9
P
10
IF (INCORRECT PARITY AND PEC ≠ 000b)
HARDWARE ERROR SIGNAL IS GENERATED
BETWEEN 10.5 ETU AND 11.5 ETU
AND DECREMENT PARITY COUNTER.
11
received with incorrect parity, the USR.PE bit is set to
1. If the parity error counter has not reached terminal
count, it is reset to the originally programmed value
upon reception of a character having the correct pari-
ty. Once the USR.PE bit signals a parity count error,
the software must re-establish any nonzero
PEC2–PEC0 setting.
The DS8007A implements an enhanced receive FIFO. If
the FIFO threshold-enable bits FTE0 and FTE1 are set
to 0, the FIFO functions as a standard FIFO that is con-
figurable to a depth of 1 to 8 characters. The T = 0 and
T = 1 protocols allow the FIFO depth to be determined
by the FCR.FL2–FCR.FL0 bits. When configurable, the
FIFO depth is equal to (FL2–FL0) + 1 (e.g., FL2–FL0 =
001b configures the FIFO depth to 2). The RBF/TBE
and FE status bits report the full and empty FIFO condi-
tions, respectively. If the receive FIFO is full (at a maxi-
mum depth of 8), the FIFO Overrun (OVR) bit is set to 1,
the new character received is lost, and the previous
FIFO contents remain undisturbed.
The received characters are read from the URR. When
the receive FIFO is enabled, reads of the URR always
access the oldest available received data. The FIFO is
initialized every time the receive mode is invoked (i.e.,
T/R bit is cleared to 0).
12
13
14
15
CHARACTER N (RETRANSMIT)
IF (CORRECT PARITY AND PE = 0)
RESET PARITY ERROR COUNTER TO
ORIGINAL PEC2–PEC0
PROGRAMMED VALUE.
Receive FIFO
P