DS8007A Maxim, DS8007A Datasheet - Page 17

• Manufacturer Part Number: DS8007A
• Description: The DS8007A multiprotocol dual smart card interface is an automotive grade, low-cost, dual smart card reader interface supporting all ISO 7816, EMV™, and GSM11-11 requirements
• Manufacturer: Maxim

Bits 7 to 0: Programmable ETU Divider Register Bits
7 to 0 (PD7 to PD0). These bits, in conjunction with the
defined UART input clock (based upon CKU,
AC2–AC0) and the prescaler selection (PSC bit), are
used to define the ETU for the UART when interfaced to
the associated card interface. The output of the
prescaler block is further divided according to the
PD7–PD0 bits as follows:
R = unrestricted read, W = unrestricted write, -n = value after reset; all bits unaffected by RIU = 0.
R = unrestricted read, W = unrestricted write, -n = value after reset; all bits unaffected by RIU = 0.
Bit 7: Reserved.
Bit 6: Disable TBE/RBF Interrupt (DISTBE/RBF). This
bit controls whether the TBE/RBF flag can generate an
interrupt on the INT pin. When this bit is cleared to 0,
an interrupt is signaled on the INT pin in response to
the TBE/RBF flag getting set. When DISTBE/RBF is set
to 1, interrupts are not generated in response to the
TBE/RBF flag. Disabling the TBE/RBF interrupt can
allow faster communication speed with the card, but
requires that a copy of TBE/RBF in register MSR be
polled to not lose priority interrupts that can occur in
register USR.
Address 02h
Address 03h
RW-0
PD7
R-0
—
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7
Multiprotocol Dual Smart Card Interface
7
DISTBE/RBF
RW-0
RW-0
PD6
6
6
DISAUX
RW-0
RW-0
PD5
5
5
PDWN
RW-0
RW-0
Programmable Divider Register (PDR)
PD4
4
4
Bit 5: Disable Auxiliary Interrupt (DISAUX). This bit
controls whether the external INTAUX pin can generate
an interrupt on the INT output pin. When this bit is
cleared to 0, a change on the INTAUX input pin results
in assertion of the INT output pin. When DISAUX is set
to 1, a change on INTAUX does not result in assertion
of the INT output pin. The INTAUXL bit is set by a
change on the INTAUX pin independent of the DISAUX
bit state. Since the INTAUX bit is set independent of the
DISAUX bit, it is advisable to read HSR (thus clearing
INTAUX) prior to clearing DISAUX to avoid an interrupt
on the INT pin. To avoid an interrupt when selecting a
different card, the DISAUX bit should be set to 1 in all
UCR2 registers.
• ETU = Prescaler output / (PD7–PD0), when
• ETU = Prescaler output / 1, when PD7–PD0 = 00h–01h
• Prescaler output / 256 is not supported
UART Control Register 2 (UCR2)
PD7–PD0 = 02h–FFh
RW-0
RW-0
SAN
PD3
3
3
AUTOC
RW-0
RW-0
PD2
2
2
RW-0
RW-0
CKU
PD1
1
1
RW-0
RW-0
PD0
PSC
0
0
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