DS8007A Maxim, DS8007A Datasheet - Page 23

• Manufacturer Part Number: DS8007A
• Description: The DS8007A multiprotocol dual smart card interface is an automotive grade, low-cost, dual smart card reader interface supporting all ISO 7816, EMV™, and GSM11-11 requirements
• Manufacturer: Maxim

Bit 7: Reserved.
Bits 6 to 4: Parity Error Count (PEC2 to PEC0). These
bits are used only for the T = 0 protocol to determine the
number of retransmission attempts that can occur in
transmit mode and the number of parity errors that can
occur before the PE bit is set to 1 to indicate that the par-
ity error limit has been reached. In transmit mode, the
DS8007A attempts to retransmit a character up to
(PEC2–PEC0) times (when NAK’d by the card) before
the PE bit is set. Retransmission attempts are automati-
cally made at 15 ETU from the previous start bit. If
PEC2–PEC0 = 000b, no retransmission attempt is made,
however, the host device can manually rewrite the char-
acter to UTR (in which case, it is re-sent as early as 13.5
ETU from the previous start bit of the error character).
In receive mode, if (PEC2–PEC0 + 1) parity errors have
been detected, the USR.PE bit is set to 1. For example,
R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 0uuu0uuub on RIU = 0.
R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 00000000b on RIU = 0.
Bits 7 to 0: UART Receive Register (Read
Operations)/UART Transmit Register (Write
Operations) (UR7/UT7 to UR0/UT0). This register is
used both as the UART transmit and receive buffer by the
host microcontroller. Received characters are always
read by the host microcontroller in direct convention,
meaning that if the CONV bit is 0, then characters
received using inverse convention are automatically
translated by the hardware. When the receive FIFO is
enabled, reads of URR always access the oldest avail-
able received data. For the synchronous mode of opera-
tion, the LSb (URR.0) reflects the state of the selected
card I/Ox line.
Writes by the host microcontroller to this register trans-
mit characters to the selected card. The host microcon-
troller should write data to UTR in direct convention
Address 0Ch
Address 0Dh
UR7/UT7
RW-0
W-0
______________________________________________________________________________________
—
UART Receive Register (URR)/UART Transmit Register (UTR)
Multiprotocol Dual Smart Card Interface
7
7
UR6/UT6
PEC2
RW-0
W-0
6
6
UR5/UT5
PEC1
RW-0
W-0
5
5
UR4/UT4
PEC0
RW-0
W-0
4
4
if PEC2–PEC0 = 000b, only one parity error needs to be
detected for the PE bit to be set; if PEC2–PEC0 = 111b,
8 parity errors must be detected, etc. If a character is
correctly received before the allowed parity error count
is reached, the parity counter is reset. For the T = 1
protocol, the parity counter is not used. The PE bit is
set whenever a parity error is detected for a received
character.
Bit 3: FIFO Threshold Enable 1 (FTE1). When this bit
and the FTE0 (UCR1.7) bit are set, the programmable
FIFO threshold feature is enabled. This bit always reads
0 for compatibility.
Bits 2 to 0: FIFO Length (FL2 to FL0). These bits
determine the depth of the receive FIFO. The receive
FIFO has depth equal to (FL2–FL0) + 1 (e.g., FIFO
depth = 2 if FL2–FL0 = 001b).
(inverse convention encoding is handled by the hard-
ware). The UTR register cannot be loaded during trans-
mission. The transmission:
For the synchronous mode of operation, only the LSb
(UTR.0) of the loaded data is transferred to the I/Ox pin
for the selected card.
• Starts at the end of the write operation (rising edge
• Starts at the end of the extra guard time if that
• Does not start if the transmission of the previous
of WR) if the previous character has been transmit-
ted and the extra guard time has been satisfied.
guard time has not been satisfied.
character is not completed (e.g., during retransmis-
sion attempts or if a transmit parity error occurs).
UR3/UT3
RW-0
FTE1
W-0
3
3
FIFO Control Register (FCR)
UR2/UT2
RW-0
FL2
W-0
2
2
UR1/UT1
RW-0
FL1
W-0
1
1
UR0/UT0
RW-0
W-0
FL0
0
0
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