73S1215F Maxim, 73S1215F Datasheet - Page 84

• Manufacturer Part Number: 73S1215F
• Description: The Teridian 73S1215F is a self-contained SoC smart card reader IC that is an ideal solution for any USB-connected ISO 7816 design
• Manufacturer: Maxim

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t1: The time from setting VCCSEL bits until VCCOK = 1.
tto: The time from setting VCCSEL bits until VCCTMR times out. At t1 (if RDYST = 1) or tto (if RDYST = 0),
activation starts. It is suggested to have RDYST = 0 and use the VCCTMR interrupt to let MPU know when
sequence is starting.
t2: time from start of activation (no external indication) until IO goes into reception mode (= 1). This is
approximately 4
t3: minimum one half of ETU period.
t4: ETU period.
Note that in Sync mode, IO as input is sampled on the rising edge of CLK. IO changes on the falling edge of CLK,
either from the card or from the 73S1215F. The RST signal to the card is directly controlled by the RSTCRD bit
(non-inverted) via the MPU and is shown as an example of a possible RST pattern.
1. Clear CLKOFF after Card is in reception mode.
2. Set RST bit.
3. Interrupt is generated when Rlength counter is MAX.
4. Read and clear Interrupt.
5. Clear RST bit.
6. Toggle TX/RXB to reset bit counter.
7. Reload RLength Counter.
TX/RXB Mode bit
Rlength Interrupt
IO reception on
RLength Count
RLenght = 1
(TX = '1')
RSTCRD
VCCOK
CLKOFF
CLKLVL
VCCSEL
Figure 22: Example of Sync Mode Operation: Generating/Reading ATR Signals
VCC
RST
CLK
RST
CLK
bits
IO
SCCLK
(or SCECLK) clock cycles.
t1
1
t1
tto
2
Figure 21: Synchronous Activation
Count MAX
t2
3
t3
6
4
5
t1. CLK wll start at least 1/2 ETU after CLKOFF is set low
when CLKLVL = 0
7
t4
Rev. 1.4