78M6612 Maxim, 78M6612 Datasheet - Page 8

• Manufacturer Part Number: 78M6612
• Description: The Teridian™ 78M6612 is a highly integrated, single-phase, power and energy measurement and monitoring system-on-chip (SoC) that includes a 32-bit compute engine (CE), an MPU core, RTC, and flash
• Manufacturer: Maxim

78M6612 Data Sheet
1.2 Analog Front End (AFE)
The AFE functions as a data acquisition system, controlled by the MPU. It consists of an input
multiplexer, a delta-sigma A/D converter, and a voltage reference. The main signals (IA, VA, IB, VB) are
sampled and the ADC counts obtained are stored in CE DRAM where they can be accessed by the CE
and, if necessary, by the MPU.
1.2.1 Input Multiplexer
The input multiplexer supports up to four input signals that are applied to pins IA, VA, IB, and VB of the
device. Additionally, using the alternate multiplexer selection, it has the ability to select temperature and
the battery voltage. The multiplexer can be operated in two modes:
•
•
The alternate multiplexer cycles are usually performed infrequently (e.g. every second or so) by the MPU.
In order to prevent disruption of the voltage tracking PLL and voltage allpass networks, VA is not
replaced in the ALT mux selections.
Missing samples due to an ALT multiplexer sequence are filled in by the CE.
In a typical application, IA and IB are connected to current sensors that sense the current on each branch
of the line voltage. VA and VB are typically connected to voltage sensors through resistor dividers. The
multiplexer control circuit is clocked by CK32, the 32.768 kHz clock from the PLL block, and launches with
each new pass of the CE program. The duration of each multiplexer state depends on the number of
8
ADC samples processed by the FIR.
EQU
During a normal multiplexer cycle, the signals from the IA, IB, VA, and VB pins are selected.
During the alternate multiplexer cycle, the temperature signal (TEMP) and the battery monitor are
selected, along with the signal sources shown in
battery, the battery monitor is enabled only with the BME bit (0x2020[6]) in the I/O RAM.
2
IA
0
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles
V A
VB
IA
IB
Regular MUX Sequence
TEMP
VBAT
VA
1
MUX_ALT
EQU
CHOP_E
MUX_DIV
Mux State
CTRL
MUX
MUX
MUX
Figure 2: AFE Block Diagram
Table 1
CROSS
CK32
IB
2
VREF_CAL
VREF_DIS
VBIAS
VREF
details the regular and alternative multiplexer sequences.
VREF
VB
FIR_DONE
3
Table
FIR_START
V3P3A
VBIAS
1. To prevent unnecessary drainage on the
TEMP
+
VREF
-
0
CONVERTER
ADC_E
∆Σ ADC
4.9MHz
ALT MUX Sequence
VA
1
Mux State
FIR_LEN
FIR
VBAT
2
DS_6612_001
VB
Rev 2
3