78M6612 Maxim, 78M6612 Datasheet - Page 11

• Manufacturer Part Number: 78M6612
• Description: The Teridian™ 78M6612 is a highly integrated, single-phase, power and energy measurement and monitoring system-on-chip (SoC) that includes a 32-bit compute engine (CE), an MPU core, RTC, and flash
• Manufacturer: Maxim

DS_6612_001
1.4 80515 MPU Core
The 78M6612 includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one
clock cycle. Using a 5 MHz (4.9152 MHz) clock results in a processing throughput of 5 MIPS. The 80515
architecture eliminates redundant bus states and implements parallel execution of fetch and execution
phases. Normally a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte
instructions are performed in a single machine cycle (MPU clock cycle). This leads to an 8x average
performance improvement (in terms of MIPS) over the Intel
frequency. Actual processor clocking speed can be adjusted to the total processing demand of the
application (measurement calculations, memory management and I/O management).
1.4.1 UARTs
The 78M6612 includes two UARTs (UART0 and UART1) that can be programmed to communicate with a
variety of external devices. The UARTs are dedicated 2-wire serial interfaces, which can communicate at
rates up to 38,400 bits/s. All UART transfers are programmable for parity enable, parity, 2 stop bits/1
stop bit and XON/XOFF option for variable communication baud rates from 300 to 38,400 bps.
1.5 On-Chip Resources
1.5.1 Oscillator
The 78M6612 oscillator drives a standard 32.768 kHz watch crystal. These crystals are accurate and do
not require a high-current oscillator circuit. The 78M6612 oscillator has been designed specifically to
handle these crystals and is compatible with their high impedance and limited power handling capability.
1.5.2 PLL and Internal Clocks
Timing for the device is derived from the 32.768 kHz oscillator output. On-chip timing functions include:
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The two general-purpose counter/timers are contained in the MPU.
The ADC master clock, CKADC, is generated by an on-chip PLL. It multiplies the oscillator output
frequency (CK32) by 150.
The CE clock frequency is always CK32 * 150, or 4.9152 MHz, where CK32 is the 32 kHz clock. The
MPU clock frequency is determined by MPU_DIV and can be 4.9152 MHz *2
varies from 0 to 7 (MPU_DIV is 0 on power-up). This makes the MPU clock scalable from 4.9152 MHz
down to 38.4 kHz. The circuit also generates a 2x MPU clock for use by the emulator. This 2x MPU
clock is not generated when ECK_DIS is asserted by the MPU.
The setting of MPU_DIV is maintained when the device transitions to BROWNOUT mode, but the time
Rev 2
base in BROWNOUT mode is 28,672 Hz.
The MPU master clock
A real time clock (RTC)
The delta-sigma sample clock.
Typical power and energy measurement functions based on the results provided by the internal
32-bit compute engine (CE) are available for the MPU as part of Maxim’s standard library. A
standard ANSI “C” 80515 application program library is available to help reduce design cycle.

8051 device running at the same clock
- MPU_DIV
Hz where MPU_DIV
78M6612 Data Sheet
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