DS28E10 Maxim, DS28E10 Datasheet - Page 11

• Manufacturer Part Number: DS28E10
• Description: The DS28E10 combines secure challenge-and-response authentication functionality based on the FIPS 180-3 specified Secure Hash Algorithm (SHA-1) with 224 bits of one-time programmable user EPROM in a single chip
• Manufacturer: Maxim

The DS28E10 requires strict protocols to ensure data
integrity. The protocol consists of four types of signaling
on one line: reset sequence with reset pulse and pres-
ence pulse, write-zero, write-one, and read-data. Except
for the presence pulse, the bus master initiates all falling
edges. The DS28E10 can communicate at two different
speeds: standard speed and overdrive speed. If not
explicitly set into the overdrive mode, the DS28E10 com-
municates at standard speed. While in overdrive mode
the fast timing applies to all waveforms.
To get from idle to active, the voltage on the 1-Wire line
needs to fall from V
from active to idle, the voltage needs to rise from 0V
past the threshold V
to make this rise is seen in Figure 9 as ε, and its dura-
tion depends on the pullup resistor (R
capacitance of the 1-Wire network attached.
Figure 9 shows the initialization sequence required to
begin any communication with the DS28E10. A reset
pulse followed by a presence pulse indicates that the
DS28E10 is ready to receive data, given the correct
ROM and memory function command. If the bus master
uses slew-rate control on the falling edge, it must pull
down the line for t
A t
mode, returning the device to standard speed. If the
DS28E10 is in overdrive mode and t
than 80Fs, the device remains in overdrive mode. If the
Figure 9. Initialization Procedure: Reset and Presence Pulse
RSTL
duration of 480Fs or longer exits the overdrive
V
IHMASTER
V
PUP
V
V
0V
IH
IL
RSTL
PUP
IH
. The time it takes for the voltage
+ t
below the threshold V
t
F
F
to compensate for the edge.
MASTER Tx "RESET PULSE"
1-Wire Signaling
RESISTOR
PUP
RSTL
) used and the
t
RSTL
is no longer
IL
. To get
1-Wire SHA-1 Authenticator
ε
device is in overdrive mode and t
and 480Fs, the device resets, but the communication
speed is undetermined.
After the bus master has released the line it goes into
receive mode. Now the 1-Wire bus is pulled to V
through the pullup resistor, or in case of a DS2482-x00
driver, by active circuitry. When the threshold V
crossed, the DS28E10 waits for t
a presence pulse by pulling the line low for t
detect a presence pulse, the master must test the logical
state of the 1-Wire line at t
The t
t
t
munication. In a mixed population network, t
be extended to minimum 480Fs at standard speed and
48Fs at overdrive speed to accommodate other 1-Wire
devices.
Data communication with the DS28E10 takes place in
time slots, which carry a single bit each. Write time slots
transport data from bus master to slave. Read time slots
transfer data from slave to master. Figure 10 illustrates
the definitions of the write and read time slots.
All communication begins with the master pulling the
data line low. As the voltage on the 1-Wire line falls below
the threshold V
generator that determines when the data line is sampled
MASTER
PDHMAX
RSTH
t
PDH
RSTH
t
is expired, the DS28E10 is ready for data com-
MSP
, t
MASTER Rx "PRESENCE PULSE"
t
PDL
PDLMAX
window must be at least the sum of
t
RSTH
IL
, the DS28E10 starts its internal timing
, and t
t
REC
MSP
Read/Write Time Slots
RECMIN
DS28E10
.
PDH
RSTL
. Immediately after
and then transmits
is between 80Fs
RSTH
PDL
should
IH
. To
PUP
17
is