DS28E10 Maxim, DS28E10 Datasheet
DS28E10
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DS28E10 Summary of contents
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... ABRIDGED DATA SHEET 219-0009; Rev 2; 4/11 General Description The DS28E10 combines secure challenge-and-response authentication functionality based on the FIPS 180-3 specified Secure Hash Algorithm (SHA-1) with 224 bits of one-time programmable user EPROM in a single chip. Once written, the memory is automatically write protected. Additionally, each device has its own guaran- teed unique 64-bit ROM identification number (ROM ID) that is factory programmed into the chip ...
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... Operating Temperature Range .......................... -40NC to +85NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... Note 11: Applies to a single DS28E10 attached to a 1-Wire line. Note 12: The earliest recognition of a negative edge is possible at t Note 13: Defines maximum possible bit rate. Equal to 1/(t Note 14: Interval after t during which a bus master is guaranteed to sample a logic there is a DS28E10 present. RSTL Minimum limit maximum limit is t PDHMAX Note 15: ε ...
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... SHA-1 computations, the device’s 64-bit ROM ID can be used to electronically identify the equipment in which the DS28E10 is used. The ROM ID also serves as node address in a multidrop 1-Wire network environment where multiple devices reside on a common 1-Wire bus and operate independently of each other ...
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... SHA-1 Authenticator 1-Wire FUNCTION CONTROL MEMORY AND SHA-1 FUNCTION CONTROL UNIT CRC-16 GENERATOR 224 BITS USER MEMORY REGISTERS DS28E10 AVAILABLE COMMANDS: DATA FIELD AFFECTED: READ ROM 64-BIT ROM ID, RC-FLAG MATCH ROM 64-BIT ROM ID, RC-FLAG SEARCH ROM 64-BIT ROM ID, RC-FLAG SKIP ROM RC-FLAG ...
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... User memory and special function registers are located in a linear address space, as shown in Figure 5. The user memory begins at address 0000h and ends at address 0017h. Refer to the full data sheet for additional information. i Button is a registered trademark of Maxim Integrated Products, Inc ...
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... Bus System The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the DS28E10 is a slave device. The bus master is typically a micro- controller. The discussion of this bus system is broken down into three topics: hardware configuration, transac- tion sequence, and 1-Wire signaling (signal types and timing) ...
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... The Overdrive-Match ROM command followed by a 64-bit ROM ID transmitted at overdrive speed allows Skip ROM [CCh] the bus master to address a specific DS28E10 on a multidrop bus and to simultaneously set it in overdrive mode. Only the DS28E10 that exactly matches the 64-bit number responds to the subsequent memory or SHA-1 function command ...
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... COMMAND DS28E10 Tx BIT 0 MASTER Tx BIT 0 DS28E10 Tx BIT 0 MASTER Tx BIT BIT 0 MATCH? BIT 0 MATCH DS28E10 Tx BIT 1 MASTER Tx BIT 1 DS28E10 Tx BIT 1 MASTER Tx BIT BIT 1 MATCH? BIT 1 MATCH DS28E10 Tx BIT 63 MASTER Tx BIT 63 DS28E10 Tx BIT 63 MASTER Tx BIT ...
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SHA-1 Authenticator TO FIGURE 8a A5h FROM FIGURE 8a RESUME COMMAND FROM FIGURE 8a TO FIGURE 8a NOTE: THE OD FLAG REMAINS THE DEVICE WAS ALREADY AT OVERDRIVE SPEED BEFORE THE OVERDRIVE-MATCH ROM ...
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... The DS28E10 can communicate at two different speeds: standard speed and overdrive speed. If not explicitly set into the overdrive mode, the DS28E10 com- municates at standard speed. While in overdrive mode the fast timing applies to all waveforms. ...
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... RESISTOR WRITE-ZERO TIME SLOT V PUP V IHMASTER RESISTOR READ-DATA TIME SLOT PUP V IHMASTER RESISTOR Figure 10. Read/Write Timing Diagrams 18 ε t SLOT MASTER t W0L t SLOT MASTER t MSR MASTER SAMPLING WINDOW δ t SLOT MASTER ε t REC t REC DS28E10 ...
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... MSRMAX the data line, the master must wait until t This guarantees sufficient recovery time t DS28E10 to get ready for the next time slot. Note that Figure 11. Programming Pulse Timing 1-Wire SHA-1 Authenticator t specified herein applies only to a single DS28E10 REC attached to a 1-Wire line ...
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... The rising-edge hold-off glitch filtering does not IH REH apply at overdrive speed. The DS28E10 uses two different types of CRCs. One CRC is an 8-bit type that is computed at the factory and REH is stored in the most significant byte of the 64-bit ROM ID number. The bus master can compute a CRC value from < ...
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... DS28E10 to determine if the ID has been received error-free. The equivalent polynomial 8 5 function of this CRC received in the true (noninverted) form. The other CRC is a 16-bit type, which is used for error detection with memory and SHA-1 commands. For details, refer to the full data sheet ...
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... ROM and memory/SHA-1 function commands. If there is more than one DS28E10 on the 1-Wire bus, this proce- dure initializes all of them at the same time. The DS28E10 might not be the only device on the 1-Wire bus. Therefore, one should be aware of unintended consequences caused by issuing Skip ROM followed ...
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... Added the Applications Information section Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2011 Maxim Integrated Products © ...