PM8803 STMicroelectronics, PM8803 Datasheet - Page 27

• Manufacturer Part Number: PM8803
• Description: High efficiency integrated IEEE 802.3at PoE-PD interface and PWM controller type 2 PSE indicator, plus support for forward active clamp topology
• Manufacturer: STMicroelectronics

PM8803
5.3
5.4
5.5
Soft-start
The DC/DC section of the PM8803 features an internal, digitally controlled, soft-start to
make sure that output voltage ramps up in a safe and controlled manner.
At the startup of the converter, the input voltage of the PWM comparator (CTL pin) is
clamped to a value which is increased cycle by cycle until it reaches the regulation voltage.
This results in a converter duty-cycle increasing from zero to the operative value in 4096
switching periods maximum.
Taking into account that the output voltage will start to increase only when the CTL pin is
higher than 1 V, effective duration of the output voltage soft-start ramp can be estimated with
the following formula:
PWM comparator / slope compensation
In typical isolated operations, current is sensed on a sense resistor Rs put between the
source of the primary side MOS and the RTN pin.
The PWM comparator produces the PWM duty cycle by comparing the Rs ramp signal on
CS with an error voltage derived from the error amplifier output.
The error amplifier output voltage at the CTL pin is attenuated by a 4:1 resistor divider
before it is presented to the PWM comparator input.
The PWM duty cycle increases with the voltage at the CTL pin. The controller output duty
cycle reduces to zero when the CTL pin voltage drops below approximately 1 V.
For duty cycles greater than 50%, current mode control loops are subject to sub-harmonic
oscillation. The PM8803 fixes the maximum duty cycle at 80% and implements a slope
compensation technique consisting of adding an additional fixed slope voltage ramp to the
signal at the CS pin. This is achieved by injecting a 45 µA sawtooth current into the current
sense signal path on an integrated 2
Additional slope compensation may be added by increasing the source impedance of the
current sense signal with an external resistor between the CS pin and the source of the
current sense signal. The net effect in this case is to increase the slope of the voltage ramp
at the PWM comparator terminals.
Current limit
The current sensed through the CS pin is compared to two fixed levels of 0.5 V and 0.7 V.
The lower level is used to perform a cycle-by-cycle current limit, terminating the PWM pulse.
If the overload persists for a duration longer than 4096 switching periods, the PWM is shut
down for the same duration before beginning a new soft-start.
At 250 kHz the allowed overcurrent duration is about 16 ms.
T
SS
[
ms
]
=
------------------------------
F
OSC
4096
[
kHz
]
⋅
Doc ID 018559 Rev 1
CTL V
----------------------------------
[ ] 1V
4V
kΩ
–
resistor.
PWM controller
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