PM8803 STMicroelectronics, PM8803 Datasheet
PM8803
Available stocks
Related parts for PM8803
PM8803 Summary of contents
Page 1
... Layer1 hardware classification, providing an indi- cation of Type 2 PSE successful detection to the rest of the system. The PM8803 has been designed to work with power either from the Ethernet cable or from an external power source such as a wall adapter, ensuring prevalence of the auxiliary source with respect to the PoE ...
Page 2
... Inrush and DC current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.6 High-voltage startup regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 bias regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 Delay time control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.4 PWM comparator / slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.5 Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.6 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 Auxiliary sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7 HTSSOP20 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2/34 Doc ID 018559 Rev 1 PM8803 ...
Page 3
... PM8803 List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 4. Thermal data Table 5. Electrical characteristics - interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 6. Electrical characteristics - SMPS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 7. Value of the external classification resistor for the different PD classes of power . . . . . . . 19 Table 8. HTSSOP20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 9 ...
Page 4
... Figure 2. Simplified application schematic for powered devices using PM8803 in synchronous flyback configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. PM8803 internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Block diagram of the DC/DC section of the PM8803 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5. Pin connections (top view Figure 6. PM8803: reference schematic of the PoE classification logic Figure 7. T2P signal when connected to PSE supporting 1-event classification . . . . . . . . . . . . . . . . 20 Figure 8 ...
Page 5
... PM8803 1 Typical application circuits and block diagrams 1.1 Application circuits Figure 1. Simplified application schematic for powered devices using PM8803 in forward active clamp configuration Typical application circuits and block diagrams Doc ID 018559 Rev 1 AM045091v1 5/34 ...
Page 6
... Typical application circuits and block diagrams Figure 2. Simplified application schematic for powered devices using PM8803 in synchronous flyback configuration 6/34 Doc ID 018559 Rev 1 PM8803 AM045092v1 ...
Page 7
... PM8803 1.2 Block diagrams Figure 3. PM8803 internal block diagram Typical application circuits and block diagrams Doc ID 018559 Rev 1 AM045093v1 7/34 ...
Page 8
... Typical application circuits and block diagrams Figure 4. Block diagram of the DC/DC section of the PM8803 8/34 Doc ID 018559 Rev 1 PM8803 AM045094v1 ...
Page 9
... PM8803 2 Pin descriptions and connection diagrams Figure 5. Pin connections (top view) Table 2. Pin descriptions Pin# Name 1 CTL RTN1 5 GAT1 GAT2 8 ARTN Pin descriptions and connection diagrams CTL RTN1 4 GAT1 GAT2 7 ARTN 8 RTN2 9 VSS 10 Function Input of the Pulse Width Modulator. ...
Page 10
... Connect the classification programming resistor from this pin to VSS. DC current limit. A resistor between this pin and VSS will set the current limit for the interface section of PM8803. It can be set to exceed the IEEE802.3at current limit. Leave the pin open for standard IEEE 802.3at applications. Rear Auxiliary startup pin. ...
Page 11
... PM8803 Table 2. Pin descriptions (continued) Pin# Name 20 T2P EP Pin descriptions and connection diagrams Function Successful 2-event classification indicator. T2P open drain signal assertion happens when powered by a PSE perform- ing a 2-event classification. T2P is an active-low signal. Exposed Pad. Connect this to a pcb copper plane to improve heat dissipation; must be electrically connected to VSS ...
Page 12
... Operative junction temperature range J T Operative ambient temperature range A 1. Package mounted on a 4-layer board ( 2 signals + 2 powers ), CU thickness 35 micron, with 6-8 vias on the exposed pad copper area connected to an inner power plane 12/34 Parameter (1) Parameter (1) Doc ID 018559 Rev 1 PM8803 Value Unit -0.3 to 100 V -0.3 to 3 -0.3 to VC+0.3 V -0 ...
Page 13
... PM8803 3.3 Electrical characteristics VDD = not loaded, Cvc = 1 µ not loaded, Cvb = 1 µF, GAT1 and GAT2 = not loaded, T Values in Bolded type apply over the full operating ambient temperature range. Table 5. Electrical characteristics - interface section Symbol Parameter Detection and classification Signature enable ...
Page 14
... Minimum VDD voltage for front aux. operations 14/34 Test conditions 150 kΩ DCCL V falling - hot-swap Mosfet DS closing. V falling - hot-swap Mosfet DS closing. Guaranteed by design V rising - hot-swap Mosfet DS opening voltage rising Doc ID 018559 Rev 1 PM8803 Min. Typ. Max. Unit 1.4 V 140 1000 mA -15 +15 % 1.35 1.50 1. ...
Page 15
... PM8803 Table 6. Electrical characteristics - SMPS section Symbol Parameter Oscillator Frequency accuracy F Frequency osc programmability Frequency range FRS voltage Delay time GAT1 to GAT2 delay time DT voltage Soft-start T Soft-start time SS Current limit Delay to output Cycle-by-cycle current limit threshold voltage Leading edge blanking ...
Page 16
... Guaranteed by design C = 3.3 nF LOAD Guaranteed by design C = 3.3 nF LOAD Guaranteed by design Always active; Guaranteed by design GAT1, GAT2 = Open VC rising VC falling mA; GAT1, GAT2 = Open GAT1, GAT2 = Open Doc ID 018559 Rev 1 PM8803 Min. Typ. Max. Unit 800 VC- VC-0.5 V 0.25 0.25 0 ...
Page 17
... Device thermal limitations could limit useful operating range. 3 The VC regulator is intended for internal use only as the startup supply of the PM8803; any additional external VC current, including the VB regulator current and external MOSFET driving current, has to be limited within the specified max current limit. ...
Page 18
... The value of the detection resistance has to be selected also taking into account the typical drop in voltage of the diode bridges. The typical value that can be used in most case is 24.9 kΩ. During detection, most of the circuits inside the PM8803 are disabled to minimize the offset current. 4.2 ...
Page 19
... Indication of successful 2-event classification The PM8803 is capable of recognizing whether it is connected to a PSE performing 1-event or 2-event physical layer classification by asserting the T2P signal. T2P is an open-drain, active-low signal which is asserted in case a successful 2-event classification event is completed. T2P will be asserted as soon as the high-voltage startup regulator output is stable. ( see ...
Page 20
... Type2, 2-event physical layer classification PSE which may allocate power either through further LLDP negotiation or directly feedthe PD with the required power. In isolated applications, the main circuits and the PM8803 are at both sides of the galvanic isolation. The T2P signal is normally connected to an optocoupler to pass the Type 2, 2-event PSE detection information to the main circuit in the PD system ...
Page 21
... During the transition from low to operating voltage, the internal UVLO is released and the hot-swap MOSFET is activated, initiating the inrush sequence. The PM8803 implements the UVLO mechanism by setting 2 internal thresholds on the voltage across the VDD-VSS pins; one is to activate the hot-swap ( switch off the hot-swap MOSFET upon detection of a supply voltage drop (V from normal operating conditions ...
Page 22
... The comparator is needed to ensure that the charge of the DC/DC input capacitor is completed, avoiding current spikes on the last portion of the charge. The PM8803 provides a default continuous current limitation of 640 mA. This is achieved by leaving the pin DCCL floating. A different DC current limit can be set by connecting a resistor R ...
Page 23
... High-voltage startup regulator The PM8803 embeds a high-voltage startup regulator to provide a controlled reference voltage of 8 the internal current mode PWM controller during its startup phase. The regulator output is connected to the VC pin as well as to the DC/DC section In normal isolated topology, the VC pin is diode-connected to the auxiliary winding of the transformer used for the flyback or forward configuration ...
Page 24
... PD interface 4 bias regulator The PM8803 features an accurate 5 V output regulator, which can be used to bias the DC/DC feedback network and the optocoupler connected to the microcontroller. A capacitor in the range of 100 nF - 2.2 µF must be connected to ARTN for stability. The regulator current is supplied from the VC pin, to take advantage of the more efficient bias from the auxiliary winding ...
Page 25
... PM8803 5 PWM controller 5.1 Oscillator The internal oscillator frequency can be programmed by connecting an external resistor R between the FRS and ARTN pins. The relationship between the oscillator frequency F and the R resistor is kHz = osc The PWM switching frequency is equal to the programmed oscillator frequency. The useful range for R Figure 11 ...
Page 26
... Figure 13. Timing relationship between output drivers as a function of DT GAT1 GAT2 26/34 is between 200 kOhm. A resistor should always 100 110 120 130 140 150 160 170 180 190 200 R [KOhm Doc ID 018559 Rev 1 PM8803 AM045102v1 DT AM045103v1 ...
Page 27
... CTL pin voltage drops below approximately 1 V. For duty cycles greater than 50%, current mode control loops are subject to sub-harmonic oscillation. The PM8803 fixes the maximum duty cycle at 80% and implements a slope compensation technique consisting of adding an additional fixed slope voltage ramp to the signal at the CS pin. This is achieved by injecting a 45 µ ...
Page 28
... Ch1: CTL signal, Ch2: 5Vout, Ch3: I input 5.6 Thermal protection The PM8803 thermal protection limit is set to 160 °C on the junction temperature and is always active. When this threshold is exceeded, the hot-swap MOSFET is opened and the PWM controller is switched off. When the junction temperature goes below about 130 °C, the converter will start automatically, without recycling the input voltage ...
Page 29
... MOSFET (VDD and RTN). This connection, together with the resistor divider on the SA pin, allows priority of the external source with respect to the PoE. Indeed, if the voltage of this pin is above the value of 1.20 V, the PM8803 will disable its PD interface section and enable the DC/DC section only. The internal hot- swap MOSFET will be opened ...
Page 30
... IEEE802.3at standard from the input (VDD to VSS ) to the the internal hot-swap MOSFET (VSS to GND) . Alternatively, split the 0.1 µF in two capacitors of 47 nF: one placed at the input terminal, the second one across the hot-swap MOSFET. 30/34 Doc ID 018559 Rev 1 PM8803 AM045105v1 ...
Page 31
... PM8803 7 HTSSOP20 package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. Table 8. HTSSOP20 mechanical data Dim ...
Page 32
... HTSSOP20 package mechanical data Figure 16. HTSSOP20 mechanical drawing 32/34 Doc ID 018559 Rev 1 PM8803 GAUGE PLANE 7292297_C ...
Page 33
... PM8803 8 Revision history Table 9. Document revision history Date 10-Mar-2011 Revision 1 Initial release. Doc ID 018559 Rev 1 Revision history Changes 33/34 ...
Page 34
... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 34/34 Please Read Carefully: © 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 018559 Rev 1 PM8803 ...