LNBH26 STMicroelectronics, LNBH26 Datasheet - Page 21

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LNBH26

Manufacturer Part Number
LNBH26
Description
Dual LNB supply and control IC with step-up and I2C interface
Manufacturer
STMicroelectronics
Datasheet

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LNBH26
7.2
S
MSB
Read mode transmission
In read mode the bytes sequence must be as follows:
Figure 12. Example of reading procedure starting with first status address 0X0
ACK = Acknowledge
S = Start
P = Stop
R/W = 1/0, Read/Write bit
X = 0/1, set the values to select the CHIP address (see
select the REGISTER address (see
b. The reading procedure can start from any register address (Status 1, 2 or Data1..4) by simply setting the X
0 0 0 1 0 0 X
MSB
CHIP ADDRESS
values in the register address byte (after the first chip address in the above figure). It can be also stopped by
the master by sending a stop condition after any acknowledge bit.
a start condition (S)
a chip address byte with the LSB bit R/W=0
the register address byte of the internal first register to be accessed
a stop condition (P)
a new master transmission with the chip address byte and the LSB bit R/W=1
after the acknowledge the LNBH26 starts to send the addressed register content. As
long as the master keeps the acknowledge LOW, the LNBH26 transmits the next
address register byte content.
the transmission is terminated when the master sets the acknowledge HIGH with a
following stop bit.
Add=0x2
DATA 1
LSB
LSB
MSB
MSB
0 0 0 0 0 X X X
MSB
REGISTER ADDRESS
STATUS 1
Add=0x0
Add=0x3
DATA 2
Doc ID 022771 Rev 1
LSB
Table 7
LSB
LSB
MSB
MSB
P
to
STATUS 2
Add=0x1
Table 12
S
Add=0x4
DATA 3
MSB
0 0 0 1 0 0 X
CHIP ADDRESS
LSB
).
Table 16
LSB
MSB
for pin selection) and to
LSB
I²C interface protocol
DATA 4
Add=0x5
LSB
AM10480v1
P
(b)
21/38

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