SRK2000 STMicroelectronics, SRK2000 Datasheet - Page 3

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SRK2000

Manufacturer Part Number
SRK2000
Description
SYNCHRONOUS RECTIFIER SMART DRIVER FOR LLC RESONANT CONVERTER
Manufacturer
STMicroelectronics
Datasheet

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SRK2000
1
Pin description
Figure 2.
Table 2.
n.
1
2
3
4
5
7
6
8
SGND
PGND
Name
DVS1
DVS2
GD2
GD1
Vcc
EN
Pin configuration
Pin description
Signal ground. Return of the bias current of the device and 0 V reference for
drain-to-source voltage monitors of both sections. Route this pin directly to
PGND.
Drain voltage threshold setting for synchronous rectifier MOSFET turn-off. UVLO
threshold programming. This pin is typically biased by either a pull-up resistor
connected to Vcc or by a resistor divider sensing Vcc. Pulling the pin to ground
disables the gate driver outputs GD1 and GD2 and can therefore be used also
as Enable input.
Drain voltage sensing for sections 1 and 2. These pins are to be connected to
the respective drain terminals of the corresponding synchronous rectifier
MOSFET via limiting resistors. When the voltage on either pin goes negative,
the corresponding synchronous rectifier MOSFET is switched on; as its
(negative) voltage exceeds a threshold defined by the EN pin, the MOSFET is
switched off. An internal logic rejects switching noise, however, extreme care in
the proper routing of the drain connection is recommended.
Gate driver output for sections 2 and 1. Each totem pole output stage is able to
drive Power MOSFETs with a peak current of 1 A source and 3.5 A sink. The
high-level voltage of these pins is clamped at about 12 V to avoid excessive gate
voltages in case the device is supplied with a high Vcc.
Power ground. Return for gate-drive currents. Route this pin to the common
point where the source terminals of both synchronous rectifier MOSFETs are
connected.
Supply voltage of the device. A small bypass capacitor (0.1 µF typ.) to SGND,
located as close to the IC’s pins as possible, may be useful to obtain a clean
supply voltage for the internal control circuitry. A similar bypass capacitor to
PGND, again located as close to the IC’s pins as possible, may be an effective
energy buffer for the pulsed gate-drive currents.
SGND
SGND
DVS1
DVS1
DVS2
DVS2
Doc ID 17811 Rev 2
EN
EN
1
1
2
2
3
3
4
4
Function
8
8
7
7
6
6
5
5
PGND
PGND
Vcc
Vcc
GD1
GD1
GD2
GD2
Pin description
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