SRK2000 STMicroelectronics, SRK2000 Datasheet - Page 12

• Manufacturer Part Number: SRK2000
• Description: SYNCHRONOUS RECTIFIER SMART DRIVER FOR LLC RESONANT CONVERTER
• Manufacturer: STMicroelectronics

Application information
12/17
slightly higher than twice the output voltage; if this exceeds the voltage rating of the internal
clamp (Vcc
appropriate value, lower than the maximum rating (25 mA) and taking the related power
dissipation into account. On the other hand, when current starts flowing into the body diode
of one MOSFET (or in the diode in parallel with the MOSFET), the drain-to-source voltage is
negative (
0.2V typ.), an internal current source I
the gate of the MOSFET is turned on. Therefore, the actual triggering threshold can be
determined by the following formula:
For instance, with R
-0.3 V.
To avoid false triggering of the gate driver, a debounce delay T
sourcing I
ns before the gate driver is turned on). This delay is not critical for the converter’s efficiency
because the initial current is close to zero or anyway much lower than the peak value.
Once the SR MOSFET has been switched on, its drain-to-source voltage drops to a value
given by the flowing current times the MOSFET R
low, the voltage drop across the R
determine an improper turn-off. To prevent this, the state machine enables the turn-off
comparator referenced to V
on the information of the duration of the previous cycle. In the first half of the conduction
cycle only an additional comparator, referenced to zero, is active to prevent the current of
the SR MOSFET from reversing, which would impair the operation of the LLC converter.
Once the threshold V
the GATE is turned off, the current again flows through the body diode causing the drain-to-
source voltage to have a negative jump, going again below V
however, prevents a false turn-on. It is worth pointing out that, due to the fact that each
MOSFET is turned on after its body diode starts conducting, the ON transition happens with
the drain-source voltage equal to the body diode forward drop; therefore there is neither a
Miller effect nor switching losses at MOSFET turn-on. Also at turn-off the switching losses
are not present, in fact, the current is always flowing from source to drain and, when the
MOSFET is switched off, it goes on flowing through the body diode (or the external diode in
parallel to the MOSFET).
Unlike at turn-on, the turn-off speed is critical to avoid current reversal on the secondary
side, especially when the converter operates above the resonance frequency, where the
current flowing through the MOSFET exhibits a very steep edge while decreasing down to
zero: the turn-off propagation T
The interlock logic, in addition to checking for consistent secondary voltage waveforms (one
MOSFET can be turned on only if the other one has a positive drain-to-source voltage >
V
one gate driver has been turned off, it cannot be turned on again before the other gate drive
has had its own on/off cycle.
The IC logic also prevents unbalanced current in the two SR MOSFETs: if one SR MOSFET
fails to turn on in one cycle, the other SR MOSFET is also not turned on in the next cycle.
DVS1,2_A
DS1,2_On
) to prevent simultaneous conduction, allows only one switching per cycle: after
≅
Z
-0.7 V); when the voltage on pins DVS1,2 reaches the threshold V
= 36 V typ.), a series resistor R
(i.e. the current sourced by the pin must exceed 50 µA for more than 250
D
DVS1,2_Off
= 2 kΩ , the triggering threshold is located at - (2 kΩ ⋅ 50 µA) - 0.2 V =
DVS1,2_Off
V
TH
Doc ID 17811 Rev 2
PD_Off
is crossed (in the second half of the conduction cycle) and
−
ON
DS(on)
=
only in the second half of the conduction cycle, based
DVS1,2_On
delay has a maximum value of 60 ns.
R
D
may exceed the turn-off threshold V
⋅
I
DVS
D
must limit the injected current below an
1
2 ,
is activated; as this current exceeds 50 µA,
On
DS(on)
+
V
DVS
. Again, since the initial current is
1
2 ,
_
TH
TH-ON
PD_On
. The interlock logic,
(= 250 ns) is used after
DVS1,2_Off
DVS1,2_TH
SRK2000
, and
(-