ST72321J9-Auto STMicroelectronics, ST72321J9-Auto Datasheet - Page 27

• Manufacturer Part Number: ST72321J9-Auto
• Description: 8-bit MCU for automotive with 60 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72321xx-Auto
Table 4.
Address
000Ch
000Dh
001Ch
001Dh
002Ch
002Dh
003Ch
003Dh
000Eh
000Fh
001Ah
001Bh
001Eh
001Fh
002Ah
002Bh
002Eh
003Ah
003Bh
003Eh
003Fh
0010h
0011h
0018h
0019h
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
to
WATCHDOG WDGCR
TIMER A
Hardware register map (continued)
FLASH
Block
Port E
Port F
MCC
SPI
ITC
I
2
C
Register label
PEDR
PEDDR
PEOR
PFDR
PFDDR
PFOR
I2CCR
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
SPIDR
SPICR
SPICSR
ISPR0
ISPR1
ISPR2
ISPR3
EICR
FCSR
SICSR
MCCSR
MCCBCR
TACR2
TACR1
TACSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Port E Data Register
Port E Data Direction Register
Port E Option Register
Port F Data Register
Port F Data Direction Register
Port F Option Register
I
I
I
I
I
I
I
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
External Interrupt Control Register
Flash Control/Status Register
Watchdog Control Register
System Integrity Control/Status Register
Main Clock Control / Status Register
Main Clock Controller: Beep Control Register
Timer A Control Register 2
Timer A Control Register 1
Timer A Control/Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
2
2
2
2
2
2
2
C Control Register
C Status Register 1
C Status Register 2
C Clock Control Register
C Own Address Register 1
C Own Address Register2
C Data Register
Doc ID 13829 Rev 1
Reserved Area (2 bytes)
Reserved Area (3 bytes)
Register name
Register and memory map
Reset status
000x 000x b R/W
xxxx x0xx b
00h
00h
FCh
FCh
FFh
FFh
FFh
FFh
FFh
FFh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
7Fh
00h
00h
00h
00h
80h
00h
80h
00h
xxh
0xh
00h
xxh
xxh
xxh
xxh
(1)
(1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
Remarks
(2)
(2)
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