ST72321J9-Auto STMicroelectronics, ST72321J9-Auto Datasheet - Page 168

• Manufacturer Part Number: ST72321J9-Auto
• Description: 8-bit MCU for automotive with 60 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321J9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

I2C bus interface (I2C)
16.7.4
168/243
Table 85.
I
Table 86.
CCR
2
Bit
Bit
2
1
0
C clock control register (CCR)
7
FM/SM
RW
7
FM/SM
BERR
Name
ARLO
GCAL
Name
SR2 register description (continued)
CCR register description
Arbitration lost
Bus error
General Call (Slave mode)
Fast/Standard I
This bit is set by hardware when the interface loses the arbitration of the bus to
another master. An interrupt is generated if ITE = 1. It is cleared by software reading
SR2 register or by hardware when the interface is disabled (PE = 0).
After an ARLO event the interface switches back automatically to Slave mode
(M/SL = 0).
The SCL line is not held low while ARLO = 1.
0: No arbitration lost detected
1: Arbitration lost detected
Note: In a Multimaster environment, when the interface is configured in Master
Receive mode it does not perform arbitration during the reception of the
Acknowledge bit. Mishandling of the ARLO bit from the I2CSR2 register may occur
when a second master simultaneously requests the same data from the same slave
and the I
instead of being set.
This bit is set by hardware when the interface detects a misplaced Start or Stop
condition. An interrupt is generated if ITE = 1. It is cleared by software reading SR2
register or by hardware when the interface is disabled (PE = 0).
The SCL line is not held low while BERR = 1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Note: If a Bus Error occurs, a Stop or a repeated Start condition should be
generated by the Master to re-synchronize communication, get the transmission
acknowledged and the bus released for further communication.
This bit is set by hardware when a general call address is detected on the bus while
ENGC = 1. It is cleared by hardware detecting a Stop condition (STOPF = 1) or
when the interface is disabled (PE = 0).
0: No general call address detected on bus
1: General call address detected on bus
This bit is set and cleared by software. It is not cleared when the interface is
disabled (PE = 0).
0: Standard I
1: Fast I
6
2
2
C mode
C master does not acknowledge the data. The ARLO bit is then left at 0
2
5
2
C mode
C mode
Doc ID 13829 Rev 1
4
CC[6:0]
Function
Function
RW
3
2
Reset value: 0000 0000 (00h)
1
ST72321xx-Auto
0