ST7263BE6 STMicroelectronics, ST7263BE6 Datasheet - Page 37

• Manufacturer Part Number: ST7263BE6
• Description: LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 32K FLASH/ROM, DFU CAPABILITY, 8-BIT ADC, WDG, TIMER, SCI and I2C
• Manufacturer: STMicroelectronics

Specifications of ST7263BE6

• 4, 8, 16 Or 32 Kbytes Program Memory: high density Flash (HDFlash), FastROM or ROM with Read-Out and Write protection

ST7263Bxx
7
Note:
Interrupts
The ST7 core may be interrupted by one of two different methods: maskable hardware
interrupts as listed in
processing flowchart is shown in
The maskable interrupts must be enabled clearing the I bit in order to be serviced. However,
disabled interrupts may be latched and processed when they are enabled (see external
interrupts subsection).
When an interrupt has to be serviced:
●
●
●
●
The interrupt service routine should finish with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.
As a consequence of the IRET instruction, the I bit will be cleared and the main program will
resume.
Priority management
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware
entering in interrupt routine.
In the case several interrupts are simultaneously pending, a hardware priority defines which
one will be serviced first (see
Non-maskable software interrupts
This interrupt is entered when the TRAP instruction is executed regardless of the state of
the I bit. It will be serviced according to the flowchart on
Interrupts and low power mode
All interrupts allow the processor to leave the Wait low power mode. Only external and
specific mentioned interrupts allow the processor to leave the Halt low power mode (refer to
the “Exit from HALT“ column in
External interrupts
The pins ITi/PAk and ITj/PBk (i=1,2; j= 5,6; k=4,5) can generate an interrupt when a rising
edge occurs on this pin. Conversely, the ITl/PAn and ITm/PBn pins (l=3,4; m= 7,8; n=6,7)
can generate an interrupt when a falling edge occurs on this pin.
Interrupt generation will occur if it is enabled with the ITiE bit (i=1 to 8) in the ITRFRE
register and if the I bit of the CC is reset.
Normal processing is suspended at the end of the current instruction execution.
The PC, X, A and CC registers are saved onto the stack.
The I bit of the CC register is set to prevent additional interrupts.
The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched (refer to
addresses).
Table 9
and a non-maskable software interrupt (TRAP). The Interrupt
Table
Doc ID 7516 Rev 8
Table
Figure
9).
9).
19.
Figure
19.
Table 9
for vector
Interrupts
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