ST7263BE6 STMicroelectronics, ST7263BE6 Datasheet - Page 157

• Manufacturer Part Number: ST7263BE6
• Description: LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 32K FLASH/ROM, DFU CAPABILITY, 8-BIT ADC, WDG, TIMER, SCI and I2C
• Manufacturer: STMicroelectronics

Specifications of ST7263BE6

• 4, 8, 16 Or 32 Kbytes Program Memory: high density Flash (HDFlash), FastROM or ROM with Read-Out and Write protection

ST7263Bxx
EXTERNAL
Figure 73
resets:
●
●
●
When the LVD is enabled:
●
●
●
Figure 73. RESET pin protection when LVD is enabled
RESET
The output of the external reset circuit must have an open-drain output to drive the ST7
reset pad. Otherwise the device can be damaged when the ST7 generates an internal
reset (LVD or watchdog).
Whatever the reset source is (internal or external), the user must ensure that the level
on the RESET pin can go below the V
Asynchronous RESET
Because the reset circuit is designed to allow the internal reset to be output in the
RESET pin, the user must ensure that the current sunk on the RESET pin is less than
the absolute maximum value specified for I
characteristics.
It is recommended not to connect a pull-up resistor or capacitor. A 10 nF pull-down
capacitor is required to filter noise on the reset line.
In case a capacitive power supply is used, it is recommended to connect a 1 MΩ pull-
down resistor to the RESET pin to discharge any residual voltage induced by the
capacitive effect of the power supply (this will add 5 µA to the power consumption of the
MCU).
Tips when using the LVD:
a)
b)
c)
Required
Check that all recommendations related to ICCCLK and reset circuit have been
applied (see notes above).
Check that the power supply is properly decoupled (100 nF + 10 µF close to the
MCU). Refer to AN1709 and AN2017. If this cannot be done, it is recommended to
put a 100 nF + 1 MΩ pull-down on the RESET pin.
The capacitors connected on the RESET pin and also the power supply are key to
avoid any start-up marginality. In most cases, steps a) and b) above are sufficient
for a robust solution. Otherwise: replace 10 nF pull-down on the RESET pin with a
5 µF to 20 µF capacitor.
and
0.01μF
Figure 74
1MΩ
Optional
show the reset circuit which protects the device against parasitic
pin. Otherwise the reset will not be taken into account internally.
Doc ID 7516 Rev 8
V
DD
R
ON
Filter
IL
max. level specified in
INJ(RESET)
GENERATOR
PULSE
in
Section Table 56.: Current
Electrical characteristics
Section Table 72.:
INTERNAL
RESET
WATCHDOG
LVD RESET
ST72XXX
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