ST72521AR9 STMicroelectronics, ST72521AR9 Datasheet - Page 133

• Manufacturer Part Number: ST72521AR9
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72521AR9

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

CONTROLLER AREA NETWORK (Cont’d)
– RESYNC. The resynchronization mode is used
– IDLE. The CAN controller looks for one of the fol-
– TRANSMISSION. Once the LOCK bit of a Buffer
to find the correct entry point for starting trans-
mission or reception after the node has gone
asynchronous either by going into the STANDBY
or bus-off states.
Resynchronization is achieved when 128 se-
quences of 11 recessive bits have been moni-
tored unless the node is not bus-off and the
FSYN bit in the CSR register is set in which case
a single sequence of 11 recessive bits needs to
be monitored.
lowing events: the RUN bit is reset, a Start Of
Frame appears on the CAN bus or the DATA7
register of the currently active page is written to.
Control/Status Register (BCSRx) has been set
and read back as such, a transmit job can be
submitted by writing to the DATA7 register. The
message with the highest priority will be transmit-
ted as soon as the CAN bus becomes idle.
Among those messages with a pending trans-
mission request, the highest priority is given to
Buffer 3 then 2 and 1. If the transmission fails due
to a lost arbitration or to an error while the NRTX
bit of the CSR register is reset, then a new trans-
mission attempt is performed. This goes on until
the transmission ends successfully or until the
job is cancelled by unlocking the buffer, by set-
ting the NRTX bit or if the node ever enters bus-
off or if a higher priority message becomes pend-
ing. The RDY bit in the BCSRx register, which
was set since the job was submitted, gets reset.
When a transmission is in progress, the BUSY bit
in the BCSRx register is set. If it ends successful-
ly then the TXIF bit in the Interrupt Status Regis-
ter (ISR) is set, else the TEIF bit is set. An
interrupt is generated in either case provided the
TXIE and TEIE bits of the ICR register are set.
Note 1: Setting the SRTE bit of the CSR register
allows transmitted messages to be simultane-
ously received when they pass the acceptance
filtering. This is particularly useful for checking
the integrity of the communication path.
RECEPTION. Once the CAN controller has syn-
chronized itself onto the bus activity, it is ready
for reception of new messages. Every incoming
message gets its identifier compared to the ac-
ceptance filters. If the bitwise comparison of the
selected bits ends up with a match for at least
one of the filters then that message is elected for
reception and a target buffer is searched for. This
buffer will be the first one - order is 1 to 3 - that
has the LOCK and RDY bits of its BCSRx regis-
ter reset.
– When no such buffer exists then an overrun
– When a buffer does exist, the accepted mes-
Up to three messages can be automatically
received without intervention from the CPU
because each buffer has its own set of status
bits, greatly reducing the reactiveness require-
ments in the processing of the receive inter-
rupts.
interrupt is generated if the ORIE bit of the ICR
register has been set. In this case the identifi-
er of the last message is made available in the
Last Identifier Register (LIDHR and LIDLR) at
least until it gets overwritten by a new identifi-
er picked-up from the bus.
sage gets written into it, the ACC bit in the
BCSRx register gets the number of the match-
ing filter, the RDY and RXIF bits get set and an
interrupt is generated if the RXIE bit in the ISR
register is set.
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