ST72325J4 STMicroelectronics, ST72325J4 Datasheet - Page 18
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ST72325J4
Manufacturer Part Number
ST72325J4
Description
8-BIT MCU WITH 16 TO 60K FLASH/ROM, ADC, CSS, FIVE TIMERS, SPI, SCI, I2C INTERFACE
Manufacturer
STMicroelectronics
Datasheet
1.ST72325K4.pdf
(197 pages)
Specifications of ST72325J4
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
Four Power Saving Modes
Halt, Active-Halt,Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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ST72325xx
Table 4. Hardware Register Map
18/197
Address
000Ah
000Bh
000Ch
000Dh
000Eh
001Ah
001Bh
001Ch
001Dh
001Eh
002Ah
002Bh
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Fh
0010h
0011h
0018h
0019h
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
WATCHDOG
FLASH
Port A
Port B
Port C
Port D
Port E
Block
Port F
SPI
ITC
I
2
C
PADR
PADDR
PAOR
PBDR
PBDDR
PBOR
PCDR
PCDDR
PCOR
PDDR
PDDDR
PDOR
PEDR
PEDDR
PEOR
PFDR
PFDDR
PFOR
I2CCR
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
SPIDR
SPICR
SPICSR
ISPR0
ISPR1
ISPR2
ISPR3
EICR
FCSR
WDGCR
SICSR
Register
Label
Port A Data Register
Port A Data Direction Register
Port A Option Register
Port B Data Register
Port B Data Direction Register
Port B Option Register
Port C Data Register
Port C Data Direction Register
Port C Option Register
Port D Data Register
Port D Data Direction Register
Port D Option Register
Port E Data Register
Port E Data Direction Register
Port E Option Register
Port F Data Register
Port F Data Direction Register
Port F Option Register
I
I
I
I
I
I
I
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
External Interrupt Control Register
Flash Control/Status Register
Watchdog Control Register
System Integrity Control/Status Register
2
2
2
2
2
2
2
C Control Register
C Status Register 1
C Status Register 2
C Clock Control Register
C Own Address Register 1
C Own Address Register2
C Data Register
Reserved Area (2 Bytes)
Register Name
000x 000x b R/W
Status
Reset
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
FFh
7Fh
xxh
0xh
00h
00h
1)
1)
1)
1)
1)
1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Remarks
2)
2)
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