ST72325J4 STMicroelectronics, ST72325J4 Datasheet - Page 154
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ST72325J4
Manufacturer Part Number
ST72325J4
Description
8-BIT MCU WITH 16 TO 60K FLASH/ROM, ADC, CSS, FIVE TIMERS, SPI, SCI, I2C INTERFACE
Manufacturer
STMicroelectronics
Datasheet
1.ST72325K4.pdf
(197 pages)
Specifications of ST72325J4
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
Four Power Saving Modes
Halt, Active-Halt,Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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ST72325xx
CLOCK CHARACTERISTICS (Cont’d)
12.5.5 Clock Security System (CSS)
Note:
1. Data based on characterization results.
12.5.6 PLL Characteristics
Note:
1. Data characterized but not tested.
The user must take the PLL jitter into account in the application (for example in serial communication or
sampling of high frequency signals). The PLL jitter is a periodic effect, which is integrated over several
CPU cycles. Therefore the longer the period of the application signal, the less it will be impacted by the
PLL jitter.
Figure 78
cies of less than 125KHz, the jitter is negligible.
Figure 78. Integrated PLL Jitter vs signal frequency
Note 1: Measurement conditions: f
154/197
+/-Jitter (%)
f
f
Δ f
SFOSC
OSC
Symbol
Symbol
CPU
1.2
0.8
0.6
0.4
0.2
/ f
1
0
CPU
shows the PLL jitter integrated on application signals in the range 125kHz to 4MHz. At frequen-
4 MHz
Safe Oscillator Frequency
PLL input frequency range
Instantaneous PLL jitter
2 MHz
Parameter
Parameter
Application Frequency
1 MHz 500 kHz 250 kHz 125 kHz
1)
1)
CPU
= 8MHz.
f
OSC
= 4 MHz.
Max
Typ
Conditions
Conditions
1
Min
Min
2
Typ
Typ
0.7
3
Max
Max
4
2
MHz
Unit
MHz
Unit
%
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