ST72324K4 STMicroelectronics, ST72324K4 Datasheet
ST72324K4
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ST72324K4 Summary of contents
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... Addressing Modes – Unsigned Multiply Instruction Development Tools ■ – Full hardware/software development package – In-Circuit Testing capability ST72324J4 1 ST72324K4 Flash 16K 512 (256) 3. -40°C to +125°C SDIP42, TQFP44 10x10,SDIP32, TQFP32 7x7 Rev. 5 NOT FOR NEW DESIGN ...
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INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 12.6.1 ...
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Timer PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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INTRODUCTION The ST72324 devices are members of the ST7 mi- crocontroller family designed for the 5V operating range. – The 32-pin devices are designed for mid-range applications – The 42/44-pin devices target the same range of applications requiring more ...
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ST72324Jx ST72324Kx 2 PIN DESCRIPTION Figure 2. 42-Pin SDIP and 44-Pin TQFP Package Pinouts RDI / PE1 (HS) PB4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4 MCO / AIN8 / PF0 BEEP ...
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PIN DESCRIPTION (Cont’d) Figure 3. 32-Pin SDIP Package Pinout OCMP1_A / AIN10 / PF4 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 AIN12 / OCMP2_B / PC0 AIN13 / OCMP1_B / PC1 ICAP2_B / (HS) PC2 ICAP1_B / (HS) PC3 ...
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ST72324Jx ST72324Kx PIN DESCRIPTION (Cont’d) For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 116. Legend / Abbreviations for Type input output supply Input level Dedicated analog input In/Output ...
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Pin n° Pin Name PC1/OCMP1_B AIN13 PC2 (HS)/ICAP2_B PC3 (HS)/ICAP1_B PC4/MISO/ICCDA PC5/MOSI/AIN14 PC6/SCK/ICCCLK 30 23 ...
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ST72324Jx ST72324Kx column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input the open drain output column, “T” defines a true open drain I/O ...
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REGISTER & MEMORY MAP As shown in Figure 5, the MCU is capable of ad- dressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations 1024 bytes of ...
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ST72324Jx ST72324Kx Table 2. Hardware Register Map Register Address Block 0000h PADR 2) 0001h Port A PADDR 0002h PAOR 0003h PBDR 2) 0004h Port B PBDDR 0005h PBOR 0006h PCDR 0007h Port C PCDDR 0008h PCOR 0009h PDADR 2) 000Ah ...
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Register Address Block Label 0031h TACR2 0032h TACR1 0033h TACSR 0034h TAIC1HR 0035h TAIC1LR 0036h TAOC1HR 0037h TAOC1LR 0038h TIMER A TACHR 0039h TACLR 003Ah TAACHR 003Bh TAACLR 003Ch TAIC2HR 003Dh TAIC2LR 003Eh TAOC2HR 003Fh TAOC2LR 0040h 0041h TBCR2 0042h ...
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ST72324Jx ST72324Kx Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents. 2. ...
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FLASH PROGRAM MEMORY 4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash non-volatile memory that can be electrically erased as a single block or by individu- al sectors and programmed on a Byte-by-Byte ba- sis using ...
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ST72324Jx ST72324Kx FLASH PROGRAM MEMORY (Cont’d) 4.4 ICC Interface ICC needs a minimum of 4 and pins to be connected to the programming tool (see These pins are: – RESET: device reset – device power ...
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... Flash memory programming can be fully custom- ized (number of bytes to program, program loca- tions, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the spe- cific microcontroller device, the user needs only to implement the ICP hardware interface on the ap- ...
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ST72324Jx ST72324Kx 5 CENTRAL PROCESSING UNIT 5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES Enable executing 63 basic instructions ■ Fast 8-bit by 8-bit multiply ■ ...
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CENTRAL PROCESSING UNIT (Cont’d) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt masks and four flags representative of the result of the instruction just executed. ...
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ST72324Jx ST72324Kx CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 FFh SP7 SP6 SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing to the ...
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SUPPLY, RESET AND CLOCK MANAGEMENT The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. An overview is ...
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ST72324Jx ST72324Kx 6.2 MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by three different source types coming from the multi- oscillator block: an external source ■ 4 crystal or ceramic resonator oscillators ■ an internal high frequency ...
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RESET SEQUENCE MANAGER (RSM) 6.3.1 Introduction The reset sequence manager includes three RE- SET sources as shown in Figure External RESET source pulse ■ Internal LVD RESET (Low Voltage Detection) ■ Internal WATCHDOG RESET ■ These sources act on ...
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ST72324Jx ST72324Kx RESET SEQUENCE MANAGER (Cont’d) The RESET pin is an asynchronous signal which plays a major role in EMS performance noisy environment recommended to follow the guidelines mentioned in the electrical characteris- tics section. 6.3.3 ...
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SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low Voltage Detector (LVD) and Auxiliary Volt- age Detector (AVD) functions managed by the SICSR register. 6.4.1 Low Voltage Detector (LVD) The Low Voltage Detector function ...
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ST72324Jx ST72324Kx SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between reference value and the V IT+(AVD) ply. The V reference value for falling voltage ...
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SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.3 Low Power Modes Mode Description No effect on SI. AVD interrupt causes the WAIT device to exit from Wait mode. HALT The CRSR register is frozen. 6.4.3.1 Interrupts The AVD interrupt event generates an interrupt ...
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ST72324Jx ST72324Kx SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write Reset Value: 000x 000x (00h) 7 AVD AVD LVD Bit 7 = Reserved, must be kept cleared. Bit 6 ...
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INTERRUPTS 7.1 INTRODUCTION The ST7 enhanced interrupt management pro- vides the following features: Hardware interrupts ■ Software interrupt (TRAP) ■ Nested or concurrent interrupt management ■ with flexible interrupt management: – software programmable nesting levels – ...
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ST72324Jx ST72324Kx INTERRUPTS (Cont’d) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: – the highest software priority interrupt is serviced, ...
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INTERRUPTS (Cont’d) 7.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see column ...
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ST72324Jx ST72324Kx INTERRUPTS (Cont’d) 7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read/Write Reset Value: 111x 1010 (xAh Bit I1, I0 Software Interrupt Priority These two bits indicate the current ...
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INTERRUPTS (Cont’d) Table 7. Dedicated Interrupt Instruction Set Instruction New Description HALT Entering Halt mode IRET Interrupt routine return JRM Jump if I1:0=11 (level 3) JRNM Jump if I1:0<>11 POP CC Pop CC from the Stack RIM Enable interrupt (level ...
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ST72324Jx ST72324Kx INTERRUPTS (Cont’d) Table 8. Interrupt Mapping Source N° Block RESET Reset TRAP Software interrupt 0 1 MCC/RTC Main clock controller time base interrupt 2 ei0 External interrupt port A3..0 3 ei1 External interrupt port F2..0 4 ei2 External ...
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Figure 21. External Interrupt Control bits PORT A3 INTERRUPT PAOR.3 PADDR.3 PA3 IPA BIT PORT F [2:0] INTERRUPTS PFOR.2 PFDDR.2 PF2 PORT B [3:0] INTERRUPTS PBOR.3 PBDDR.3 PB3 IPB BIT PORT B4 INTERRUPT PBOR.4 PBDDR.4 PB4 EICR IS20 IS21 SENSITIVITY ...
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ST72324Jx ST72324Kx INTERRUPTS (Cont’d) 7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read/Write Reset Value: 0000 0000 (00h) 7 IS11 IS10 IPB IS21 IS20 Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied ...
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INTERRUPTS (Cont’d) Table 9. Nested Interrupts Register Map and Reset Values Address Register 7 (Hex.) Label 0024h I1_3 ISPR0 1 Reset Value 0025h I1_7 ISPR1 1 Reset Value 0026h ISPR2 I1_11 1 Reset Value 0027h ISPR3 Reset Value 1 EICR ...
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ST72324Jx ST72324Kx 8 POWER SAVING MODES 8.1 INTRODUCTION To give a large measure of flexibility to the applica- tion in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 22): SLOW, WAIT (SLOW ...
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POWER SAVING MODES (Cont’d) 8.3 WAIT MODE WAIT mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. During WAIT ...
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ST72324Jx ST72324Kx POWER SAVING MODES (Cont’d) 8.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two low- est power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruc- tion. The decision to enter ...
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POWER SAVING MODES (Cont’d) 8.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is ...
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ST72324Jx ST72324Kx POWER SAVING MODES (Cont’d) 8.4.2.1 Halt Mode Recommendations – Make sure that an external event is available to wake up the microcontroller from Halt mode. – When using an external interrupt to wake up the microcontroller, reinitialize the ...
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I/O PORTS 9.1 INTRODUCTION The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe- ripherals. An I/O ...
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ST72324Jx ST72324Kx I/O PORTS (Cont’d) Figure 29. I/O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS ALTERNATE ENABLE DR DDR OR If implemented OR SEL DDR SEL DR SEL 1 0 EXTERNAL INTERRUPT SOURCE ( Table 10. I/O ...
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I/O PORTS (Cont’d) Table 11. I/O Port Configurations NOT IMPLEMENTED IN V TRUE OPEN DRAIN I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V I/O PORTS PAD Notes: 1. ...
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ST72324Jx ST72324Kx I/O PORTS (Cont’d) CAUTION: The alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used ...
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I/O PORTS (Cont’d) 9.5.1 I/O Port Implementation The I/O port register configurations are summa- rised as follows. Standard Ports PA5:4, PC7:0, PD5:0, PE1:0, PF7:6, 4 MODE floating input pull-up input open drain output push-pull output Interrupt Ports PB4, PB2:0, PF1:0 ...
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ST72324Jx ST72324Kx I/O PORTS (Cont’d) Table 13. I/O Port Register Map and Reset Values Address Register 7 (Hex.) Label Reset Value of all I/O port registers 0000h PADR 0001h PADDR MSB 0002h PAOR 0003h PBDR 0004h PBDDR MSB 0005h PBOR ...
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ON-CHIP PERIPHERALS 10.1 WATCHDOG TIMER (WDG) 10.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program ...
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ST72324Jx ST72324Kx WATCHDOG TIMER (Cont’d) 10.1.4 How to Program the Watchdog Timeout Figure 32 shows the linear relationship between the 6-bit value to be loaded in the Watchdog Coun- ter (CNT) and the resulting timeout duration in mil- liseconds. This ...
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WATCHDOG TIMER (Cont’d) Figure 33. Exact Timeout Duration (t WHERE (LSB + 128 min0 OSC2 t = 16384 x t max0 OSC2 t = 125ns MHz OSC2 OSC2 CNT = Value ...
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ST72324Jx ST72324Kx WATCHDOG TIMER (Cont’d) 10.1.5 Low Power Modes Mode Description SLOW No effect on Watchdog. WAIT No effect on Watchdog. OIE bit in WDGHALT bit MCCSR in Option register Byte 0 HALT 0 1 10.1.6 Hardware Watchdog Option If ...
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Table 14. Watchdog Timer Register Map and Reset Values Address Register 7 (Hex.) Label WDGCR WDGA 002Ah Reset Value ST72324Jx ST72324Kx ...
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ST72324Jx ST72324Kx 10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) The Main Clock Controller consists of three differ- ent functions: a programmable CPU clock prescaler ■ a clock-out signal to supply external devices ■ a real time ...
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d) 10.2.5 Low Power Modes Mode Description No effect on MCC/RTC peripheral. WAIT MCC/RTC interrupt cause the device to exit from WAIT mode. No effect on MCC/RTC counter (OIE bit is ACTIVE- set), ...
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ST72324Jx ST72324Kx MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d) Bit 0 = OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the MCCSR register. It indicates when set that the main oscillator has ...
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TIMER 10.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input sig- nals (input capture) ...
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ST72324Jx ST72324Kx 16-BIT TIMER (Cont’d) Figure 35. Timer Block Diagram f CPU 8 high EXEDG 1/2 COUNTER 1/4 REGISTER 1/8 ALTERNATE EXTCLK pin COUNTER REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 (Control/Status Register) ICIE OCIE TOIE FOLV2 (See ...
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TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MS Byte At t0 Other instructions Returns the buffered Read At t0 +∆t LS Byte value ...
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ST72324Jx ST72324Kx 16-BIT TIMER (Cont’d) Figure 36. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 37. Counter Timing Diagram, internal clock divided by 4 CPU CLOCK INTERNAL ...
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TIMER (Cont’d) 10.3.3.3 Input Capture In this section, the index, i, may because there are 2 input capture functions in the 16-bit timer. The two 16-bit input capture registers (IC1R and IC2R) are used to ...
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ST72324Jx ST72324Kx 16-BIT TIMER (Cont’d) Figure 39. Input Capture Block Diagram ICAP1 pin EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 16-BIT 16-BIT FREE RUNNING COUNTER Figure 40. Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi ...
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TIMER (Cont’d) 10.3.3.4 Output Compare In this section, the index, i, may because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate ...
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ST72324Jx ST72324Kx 16-BIT TIMER (Cont’d) Notes: 1. After a processor write cycle to the OCiHR reg- ister, the output compare function is inhibited until the OCiLR register is also written the OCiE bit is not set, the OCMPi ...
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TIMER (Cont’d) Figure 42. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) Figure 43. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER ...
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ST72324Jx ST72324Kx 16-BIT TIMER (Cont’d) 10.3.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses ...
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TIMER (Cont’d) Figure 44. One Pulse Mode Timing Example IC1R 01F8 COUNTER ICAP1 OCMP1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1 Figure 45. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions FFFC FFFD FFFE COUNTER 34E2 OCMP1 compare2 ...
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ST72324Jx ST72324Kx 16-BIT TIMER (Cont’d) 10.3.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. Pulse Width Modulation ...
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TIMER (Cont’d) 10.3.4 Low Power Modes Mode No effect on 16-bit Timer. WAIT Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is ...
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ST72324Jx ST72324Kx 16-BIT TIMER (Cont’d) 10.3.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and ...
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TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal ...
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ST72324Jx ST72324Kx 16-BIT TIMER (Cont’d) CONTROL/STATUS REGISTER (CSR) Read Only (except bit 2 R/W) Reset Value: xxxx x0xx (xxh) 7 ICF1 OCF1 TOF ICF2 OCF2 TIMD Bit 7 = ICF1 Input Capture Flag input capture (reset value). ...
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TIMER (Cont’d) INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). 7 MSB INPUT ...
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ST72324Jx ST72324Kx 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB Note: In Flash ...
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ALTERNATE COUNTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. 7 MSB ALTERNATE COUNTER (ACLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit ...
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ST72324Jx ST72324Kx 16-BIT TIMER (Cont’d) Table 17. 16-Bit Timer Register Map and Reset Values Address Register (Hex.) Label Timer A: 32 CR1 ICIE Timer B: 42 Reset Value Timer A: 31 CR2 OC1E Timer B: 41 Reset Value Timer A: ...
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SERIAL PERIPHERAL INTERFACE (SPI) 10.4.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI interface can not ...
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ST72324Jx ST72324Kx SERIAL PERIPHERAL INTERFACE (Cont’d) – SS: Slave select: This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves indi- vidually and to avoid contention on the data lines. Slave SS inputs can ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM ...
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ST72324Jx ST72324Kx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 50). Note: The idle state of SCK must correspond to the polarity selected ...
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ST72324Jx ST72324Kx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.5 Error Flags 10.4.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: – The MODF bit is set ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.5.4 Single Master Systems A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see Figure 52). The master device selects the individual slave de- vices by ...
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ST72324Jx ST72324Kx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.6 Low Power Modes Mode Description No effect on SPI. WAIT SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.4.8 Register Description CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by software. 0: Interrupt ...
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ST72324Jx ST72324Kx SERIAL PERIPHERAL INTERFACE (Cont’d) CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) 7 SPIF WCOL OVR MODF Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only). This bit is set by ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) Table 19. SPI Register Map and Reset Values Address Register 7 (Hex.) Label SPIDR MSB 0021h Reset Value SPICR SPIE 0022h Reset Value SPICSR SPIF 0023h Reset Value SPE SPR2 MSTR ...
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ST72324Jx ST72324Kx 10.5 SERIAL COMMUNICATIONS INTERFACE (SCI) 10.5.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI of- fers a very ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 53. SCI Block Diagram Write Transmit Data Register (TDR) TDO Transmit Shift Register RDI TRANSMIT CONTROL CR2 TIE TCIE RIE SCI INTERRUPT CONTROL TRANSMITTER CLOCK f CPU Read Received Data Register (RDR SCID ...
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ST72324Jx ST72324Kx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 1. It contains six dedicated reg- isters: – Two control registers (SCICR1 & SCICR2) – A status register (SCISR) ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.4.2 Transmitter The transmitter can send data words of either bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the ...
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ST72324Jx ST72324Kx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.4.3 Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 55. SCI Baud Rate and Extended Prescaler Block Diagram EXTENDED PRESCALER TRANSMITTER RATE CONTROL EXTENDED TRANSMITTER PRESCALER REGISTER EXTENDED RECEIVER PRESCALER REGISTER EXTENDED PRESCALER RECEIVER RATE CONTROL f CPU /PR /16 SCP1 CONVENTIONAL BAUD RATE ...
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ST72324Jx ST72324Kx SERIAL COMMUNICATIONS INTERFACE (Cont’d) Framing Error A framing error is detected when: – The stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. – A break is received. ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.4.7 Parity Control Parity control (generation of parity bit in transmis- sion and parity checking in reception) can be ena- bled by setting the PCE bit in the SCICR1 register. Depending on the frame length defined ...
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ST72324Jx ST72324Kx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.4.9 Clock Deviation Causes The causes which contribute to the total deviation are: – Deviation due to transmitter error (Local TRA oscillator error of the transmitter or the trans- mitter is transmitting ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.5 Low Power Modes Mode Description No effect on SCI. WAIT SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. HALT In Halt mode, the SCI stops transmitting/re- ceiving until Halt ...
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ST72324Jx ST72324Kx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.5.7 Register Description STATUS REGISTER (SCISR) Read Only Reset Value: 1100 0000 (C0h) 7 TDRE TC RDRF IDLE OR Bit 7 = TDRE Transmit data register empty. This bit is set by hardware when ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (SCICR1) Read/Write Reset Value: x000 0000 (x0h SCID M WAKE Bit Receive data bit 8. This bit is used to store the 9th bit of the received ...
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ST72324Jx ST72324Kx SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 2 (SCICR2) Read/Write Reset Value: 0000 0000 (00h) 7 TIE TCIE RIE ILIE TE Bit 7 = TIE Transmitter interrupt enable. This bit is set and cleared by software. 0: Interrupt is ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (SCIDR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data char- acter, depending on whether it is read from or writ- ten to. 7 DR7 DR6 DR5 DR4 DR3 The Data register performs ...
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ST72324Jx ST72324Kx SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (SCIERPR) Read/Write Reset Value: 0000 0000 (00h) Allows setting of the Extended Prescaler rate divi- sion factor for the receive circuit. 7 ERPR ERPR ERPR ERPR ERPR 7 6 ...
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SERIAL COMMUNICATION INTERFACE (Cont’d) Table 22. SCI Register Map and Reset Values Address Register 7 (Hex.) Label SCISR TDRE 0050h Reset Value 1 SCIDR MSB 0051h Reset Value x SCIBRR SCP1 0052h Reset Value 0 SCICR1 R8 0053h Reset Value ...
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ST72324Jx ST72324Kx 10.6 10-BIT A/D CONVERTER (ADC) 10.6.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 10-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog input ...
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A/D CONVERTER (ADC) (Cont’d) 10.6.3 Functional Description The conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (V ) ...
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ST72324Jx ST72324Kx 10-BIT A/D CONVERTER (ADC) (Cont’d) 10.6.6 Register Description CONTROL/STATUS REGISTER (ADCCSR) Read/Write (Except bit 7 read only) Reset Value: 0000 0000 (00h) 7 EOC SPEED ADON 0 CH3 Bit 7 = EOC End of Conversion This bit is ...
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A/D CONVERTER (Cont’d) Table 23. ADC Register Map and Reset Values Address Register 7 (Hex.) Label ADCCSR EOC 0070h Reset Value 0 ADCDRH D9 0071h Reset Value 0 ADCDRL 0072h Reset Value SPEED ADON 0 ...
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ST72324Jx ST72324Kx 11 INSTRUCTION SET 11.1 CPU ADDRESSING MODES The CPU features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld ...
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INSTRUCTION SET OVERVIEW (Cont’d) 11.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W Interrupt Wait For ...
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ST72324Jx ST72324Kx INSTRUCTION SET OVERVIEW (Cont’d) 11.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an ...
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INSTRUCTION SET OVERVIEW (Cont’d) 11.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch ...
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ST72324Jx ST72324Kx INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is ...
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INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack RCF Reset ...
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ST72324Jx ST72324Kx 12 ELECTRICAL CHARACTERISTICS 12.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred 12.1.1 Minimum and Maximum values Unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- ...
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ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- 12.2.1 Voltage Characteristics Symbol ...
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ST72324Jx ST72324Kx 12.2.3 Thermal Characteristics Symbol T Storage temperature range STG T Maximum junction temperature (see J 12.3 OPERATING CONDITIONS 12.3.1 Operating Conditions Symbol Parameter f Internal clock frequency CPU Operating voltage (except Flash Write/ Erase Operating Voltage ...
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OPERATING CONDITIONS (Cont’d) 12.4 LVD/AVD CHARACTERISTICS 12.4.1 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for T Symbol Parameter Reset release threshold V IT+(LVD) (V rise) DD Reset generation threshold V IT-(LVD) (V fall ...
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ST72324Jx ST72324Kx 12.5 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consump- tion, the two current ...
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SUPPLY CURRENT CHARACTERISTICS (Cont’d) 12.5.1.1 Power Consumption vs f Figure 61. Typical I in RUN mode DD 8MHz 9 4MHz 8 2MHz 1MHz 4.4 4.8 Vdd (V) Figure 62. Typical I ...
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ST72324Jx ST72324Kx SUPPLY CURRENT CHARACTERISTICS (Cont’d) 12.5.2 Supply and Clock Managers The previous current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device ...
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SUPPLY CURRENT CHARACTERISTICS (Cont’d) 12.5.3 On-Chip Peripherals T = 25°C f =4MHz. A CPU Symbol I 16-bit Timer supply current DD(TIM) I SPI supply current DD(SPI) I SCI supply current DD(SCI) I ADC supply current when converting DD(ADC) Notes: 1. ...
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ST72324Jx ST72324Kx 12.6 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V 12.6.1 General Timings Symbol Parameter t Instruction cycle time c(INST) Interrupt reaction time t = ∆t v(IT v(IT) c(INST) 12.6.2 External Clock Source ...
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CLOCK AND TIMING CHARACTERISTICS (Cont’d) 12.6.3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external ...
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ST72324Jx ST72324Kx CLOCK AND TIMING CHARACTERISTICS (Cont’d) Typical Ceramic Resonators (information for guidance only) Oscil. 3) Reference LP CSA2.00MG MP CSA4.00MG MS CSA8.00MTZ 4) HS CSA16.00MXZ040 Notes: 1. Resonator characteristics given by the ceramic resonator manufacturer the ...
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CLOCK CHARACTERISTICS (Cont’d) 12.6.4 RC Oscillators Symbol Parameter Internal RC oscillator frequency f OSC (RCINT) See Figure 67 Figure 67. Typical f OSC(RCINT) 4 3.8 3.6 3.4 3 (°C) A Conditions T =25°C, V =5V ...
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ST72324Jx ST72324Kx CLOCK CHARACTERISTICS (Cont’d) 12.6.5 PLL Characteristics Symbol Parameter f PLL input frequency range OSC ∆ Instantaneous PLL jitter CPU CPU Note: 1. Data characterized but not tested. The user must take the PLL jitter into ...
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MEMORY CHARACTERISTICS 12.7.1 RAM and Hardware Registers Symbol Parameter V Data retention mode RM 12.7.2 FLASH Memory DUAL VOLTAGE HDFLASH MEMORY Symbol Parameter f Operating frequency CPU V Programming voltage Supply current ...
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ST72324Jx ST72324Kx 12.8 EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba- sis during product characterization. 12.8.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product ...
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EMC CHARACTERISTICS (Cont’d) 12.8.2 Electro Magnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the ...
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... Dynamic latch-up class Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec- ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). ...
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I/O PORT PIN CHARACTERISTICS 12.9.1 General Characteristics Subject to general operating conditions for V Symbol Parameter Input low level voltage (standard voltage devices) V Input high level voltage IH V Schmitt trigger voltage hysteresis hys Injected ...
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ST72324Jx ST72324Kx I/O PORT PIN CHARACTERISTICS (Cont’d) 12.9.2 Output Driving Current Subject to general operating conditions for V Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 71) ...
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I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 74. Typical V vs ...
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ST72324Jx ST72324Kx 12.10 CONTROL PIN CHARACTERISTICS 12.10.1 Asynchronous RESET Pin Subject to general operating conditions for V Symbol Parameter V Schmitt trigger voltage hysteresis hys V Input low level voltage IL V Input high level voltage IH V Output low ...
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CONTROL PIN CHARACTERISTICS (Cont’d) Figure 77. RESET pin protection when LVD is enabled. Recommended EXTERNAL RESET 0.01µF Figure 78. RESET pin protection when LVD is disabled. Recommended V DD 0.01µF USER EXTERNAL RESET CIRCUIT 0.01µF Required 1. The reset network ...
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ST72324Jx ST72324Kx CONTROL PIN CHARACTERISTICS (Cont’d) 12.10.2 ICCSEL/V Pin PP Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH I Input leakage current L Figure 79. Two typical ...
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TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for V Refer to I/O port characteristics for more details on the input/output alternate function characteristics (out- put compare, input capture, external clock, PWM output...). Data based on design simulation and/or ...
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ST72324Jx ST72324Kx 12.12 COMMUNICATION INTERFACE CHARACTERISTICS 12.12.1 SPI - Serial Peripheral Interface Subject to general operating conditions for V design simulation and/or characterisation results, not tested in production. When no communication is on-going the data output line of the SPI ...
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 81. SPI Slave Timing Diagram with CPHA=1 SS INPUT t su(SS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 t w(SCKH) t a(SO) t w(SCKL) see MISO OUTPUT HZ note 2 t su(SI) MOSI INPUT Figure 82. SPI Master ...
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ST72324Jx ST72324Kx 12.13 10-BIT ADC CHARACTERISTICS Subject to general operating conditions for V Symbol Parameter f ADC clock frequency ADC V Analog reference voltage AREF V Conversion voltage range AIN Positive input leakage current for analog I 2) lkg input ...
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ADC CHARACTERISTICS (Cont’d) Figure 83. R max AIN ADC (pF) PARASITIC Figure 85. Typical A/D Converter Application R AIN V AIN Notes represents ...
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ST72324Jx ST72324Kx ADC CHARACTERISTICS (Cont’d) 12.13.1 Analog Power Supply and Reference Pins Depending on the MCU pin count, the package may feature separate V AREF power supply pins. These pins supply power to the A/D converter cell and function as ...
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ADC CHARACTERISTICS (Cont’d) 12.13.3 ADC Accuracy 1) Conditions: V =5V DD Symbol Parameter Total unadjusted error Offset error Gain Error G Differential linearity error | ...
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ST72324Jx ST72324Kx 13 PACKAGE CHARACTERISTICS 13.1 PACKAGE MECHANICAL DATA Figure 88. 44-Pin Thin Quad Flat Package D D1 Figure 89. 32-Pin Thin Quad Flat Package D D1 146/164 ...
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PACKAGE MECHANICAL DATA (Cont’d) Figure 90. 42-Pin Plastic Dual In-Line Package, Shrink 600-mil Width - b2 D Figure 91. 32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width ...
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ST72324Jx ST72324Kx 13.2 THERMAL CHARACTERISTICS Symbol Package thermal resistance (junction to ambient) R thJA P Power dissipation D T Maximum junction temperature Jmax Notes: 1. The power dissipation is obtained from the formula P and P is the port power ...
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SOLDERING INFORMATION In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level in- terconnect. The category of second level intercon- nect is marked on the package and on the ...
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ST72324Jx ST72324Kx 14 ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION 14.1 FLASH OPTION BYTES STATIC OPTION BYTE 0 7 WDG 1 Default The option bytes allows the hardware configura- tion of the microcontroller to be selected. They ...
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ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) OPTION BYTE 1 OPT7= PKG1 Pin package selection bit This option bit selects the package. Version Selected Package J TQFP44 / SDIP42 K TQFP32 / SDIP32 Note: On the chip, each I/O port ...
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ST72324Jx ST72324Kx DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) 14.2 FLASH DEVICE ORDERING INFORMATiON With the objective of continuous improvement developing new ST72F324B devices and is transferring the production to higher capacity fabs. Refer to the following tables for ...
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DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) Table 26. Standard and Industrial ST72F324 Flash Order Codes Part Number ST72F324K2B5 ST72F324K4B5 ST72F324K6B5 ST72F324J6B5 ST72F324K6T5 ST72F324K2T6 ST72F324K4T6 ST72F324K6T6 ST72F324K2T3 ST72F324K4T3 ST72F324K6T3 ST72F324J6T5 ST72F324J2T6 ST72F324J4T6 ST72F324J6T6 ST72F324J2T3 ST72F324J4T3 ST72F324J6T3 Package Flash Memory (KBytes) SDIP32 ...
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ST72324Jx ST72324Kx 14.3 SILICON IDENTIFICATION The various ST72F324, ST72324B devices are identifiable both by the last letter of the Trace code marked on the device package and by the last 3 digits of the Internal Sales Type printed on the ...
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... DEVELOPMENT TOOLS STMicroelectronics offers a range of hardware and software development tools for the ST7 micro- controller family. Full details of tools available for the ST7 from third party manufacturers can be ob- tain from the STMicroelectronics Internet site: ➟ http//:mcu.st.com. Tools from these manufacturers include C compli- ers, emulators and gang programmers ...
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ST72324Jx ST72324Kx 14.4.1 Socket and Emulator Information For information on the type of socket that is sup- plied with the emulator, refer to the suggested list of sockets in Table 29. Note: Before designing the board layout rec- ...
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ST7 APPLICATION NOTES Table 30. ST7 Application Notes IDENTIFICATION DESCRIPTION APPLICATION EXAMPLES AN1658 SERIAL NUMBERING IMPLEMENTATION AN1720 MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS AN1755 A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555 EXAMPLE DRIVERS AN 969 SCI COMMUNICATION ...
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ST72324Jx ST72324Kx Table 30. ST7 Application Notes IDENTIFICATION DESCRIPTION AN 978 ST7 VISUAL DEVELOP SOFTWARE KEY DEBUGGING FEATURES AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE AN 985 EXECUTING CODE IN ST7 RAM AN 986 USING THE INDIRECT ...
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KNOWN LIMITATIONS 15.1 ALL DEVICES 15.1.1 External RC option The External RC clock source option described in previous datasheet revisions is no longer support- ed and has been removed from this specification. 15.1.2 CSS Function The Clock Security System ...
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ST72324Jx ST72324Kx KNOWN LIMITATIONS (Cont’d) To avoid this, a semaphore is set to '1' before checking the level change. The semaphore is changed to level '0' inside the interrupt routine. When a level change is detected, the semaphore status is ...
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JP while_loop .call_routine ; entry to call_routine PUSH A PUSH X PUSH CC .ext1_rt ; entry to interrupt routine LD A,#$00 LD sema,A IRET 15.1.7 16-bit Timer PWM Mode In PWM mode, the first PWM pulse is missed after writing ...
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ST72324Jx ST72324Kx 16 IMPORTANT NOTES ON ST72F324B FLASH DEVICES: With the objective of continuous improvement, ST has developed new ST72F324B devices. These devices are fully compatible with all ROM features and provide an improved price/performance ratio compared to the ST72F324 ...
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REVISION HISTORY Table 31. Revision History Date Revision Merged ST72F324 Flash with ST72324B ROM datasheet. Vt POR max modified in Added 05-May-2004 2.0 Modified V Modified I INJ for PB0 in Added Modified Removed Clock Security System (CSS) throughout ...
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... ST72324Jx ST72324Kx Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...