ST7LITEU09 STMicroelectronics, ST7LITEU09 Datasheet - Page 53

• Manufacturer Part Number: ST7LITEU09
• Description: ST7ULTRALITE - 8-BIT MCU WITH 2K SINGLE VOLTAGE FLASH MEMORY, ADC, TIMERS
• Manufacturer: STMicroelectronics

Specifications of ST7LITEU09

• 2k Bytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C
• 128 Bytes Data Eeprom. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C
• Clock Sources: internal trimmable 8MHz RC oscillator, internal low power, low frequency RC oscillator or external clock
• Five Power Saving Modes: Halt, Auto Wake Up from Halt, Active-Halt, Wait and Slow
• One 8-bit Lite Timer (lt) With Prescaler Including: watchdog, 1 realtime base and 1 input capture

ST7LITEU05 ST7LITEU09
9.4
9.4.1
Caution:
Active-halt and Halt modes
Active-Halt and Halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘Halt’ instruction. The decision to enter either in Active-
Halt or Halt mode is given by the LTCSR/ATCSR register status as shown in the following
table:
Table 16.
Active-halt mode
Active-halt mode is the lowest power consumption mode of the MCU with a real time clock
available. It is entered by executing the ‘Halt’ instruction when active halt mode is enabled.
The MCU can exit Active-halt mode on reception of a Lite Timer / AT Timer interrupt or a
Reset.
●
●
When entering Active-Halt mode, the I bit in the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active-halt mode, only the main oscillator and the selected timer counter (LT/AT) are
running to keep a wake-up time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
As soon as Active-halt is enabled, executing a HALT instruction while the Watchdog is active
does not generate a Reset if the WDGHalt bit is reset.
This means that the device cannot spend more than a defined delay in this power saving
mode.
Figure 25. Active-halt timing overview
LTCSR TBIE
When exiting Active-halt mode by means of a Reset, a 256 or 512 CPU cycle delay
occurs. After the start up delay, the CPU resumes operation by fetching the reset vector
which woke it up (see
When exiting Active-Halt mode by means of an interrupt, the CPU immediately
resumes operation by servicing the interrupt vector which woke it up (see
bit
0
0
0
1
x
Enabling/disabling Active-halt and Halt modes
ATCSR OVFIE
bit
x
0
1
x
1
[Active Halt Enabled]
Figure
INSTRUCTION
RUN
HALT
ATCSRCK1 bit ATCSRCK0 bit
ACTIVE
26).
HALT
1
0
x
x
x
256 OR 512 CPU
CYCLE DELAY
INTERRUPT
RESET
OR
1)
VECTOR
0
1
1
x
x
FETCH
RUN
Active-Halt mode disabled
Active-Halt mode enabled
Power saving modes
Meaning
Figure
53/139
26).