ST7263BH2 STMicroelectronics, ST7263BH2 Datasheet - Page 56

• Manufacturer Part Number: ST7263BH2
• Description: LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 32K FLASH/ROM, DFU CAPABILITY, 8-BIT ADC, WDG, TIMER, SCI and I2C
• Manufacturer: STMicroelectronics

Specifications of ST7263BH2

• 4, 8, 16 Or 32 Kbytes Program Memory: high density Flash (HDFlash), FastROM or ROM with Read-Out and Write protection

On-chip peripherals
11.1.7
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HALT instruction
If the Watchdog reset on HALT option is selected by option byte, a HALT instruction causes
an immediate reset generation if the Watchdog is activated (WDGA bit is set).
Using Halt mode with the WDG (option)
If the Watchdog reset on HALT option is not selected by option byte, the Halt mode can be
used when the watchdog is enabled.
In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the
WDG stops counting and is no longer able to generate a reset until the microcontroller
receives an external interrupt or a reset.
If an external interrupt is received, the WDG restarts counting after 4096 CPU clocks. If a
reset is generated, the WDG is disabled (reset state).
Recommendations:
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Interrupts
None.
Make sure that an external event is available to wake up the microcontroller from Halt
mode.
Before executing the HALT instruction, refresh the WDG counter, to avoid an
unexpected WDG reset immediately after waking up the microcontroller.
When using an external interrupt to wake up the microcontroller, reinitialize the
corresponding I/O as “Input Pull-up with interrupt” before executing the HALT
instruction. The main reason for this is that the I/O may be wrongly configured due to
external interference or by an unforeseen logical condition.
For the same reason, reinitialize the level sensitiveness of each external interrupt as a
precautionary measure.
The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction
due to a program counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in ROM with the value
0x8E.
As the HALT instruction clears the I bit in the CC register to allow interrupts, the user
may choose to clear all pending interrupt bits before executing the HALT instruction.
This avoids entering other peripheral interrupt routines after executing the external
interrupt routine corresponding to the wakeup event (reset or external interrupt).
Doc ID 7516 Rev 8
ST7263Bxx