ST7263BH2 STMicroelectronics, ST7263BH2 Datasheet - Page 102

• Manufacturer Part Number: ST7263BH2
• Description: LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 32K FLASH/ROM, DFU CAPABILITY, 8-BIT ADC, WDG, TIMER, SCI and I2C
• Manufacturer: STMicroelectronics

Specifications of ST7263BH2

• 4, 8, 16 Or 32 Kbytes Program Memory: high density Flash (HDFlash), FastROM or ROM with Read-Out and Write protection

On-chip peripherals
Note:
102/186
To avoid spurious clearing of some bits, it is recommended to clear them using a load
instruction where all bits which must not be altered are set, and all bits to be cleared are
reset. Avoid read-modify-write instructions like AND, XOR.
Interrupt Mask register (IMR)
These bits are mask bits for all interrupt condition bits included in the ISTR. Whenever one
of the IMR bits is set, if the corresponding ISTR bit is set, and the I bit in the CC register is
cleared, an interrupt request is generated. For an explanation of each bit, please refer to the
corresponding bit description in ISTR.
Reset value: 0000 0000 (00h)
SUSPM
7
2 ESUSP End suspend mode.
1 RESET USB reset.
0 SOF Start of frame.
DOVRM
This bit is set by hardware when, during suspend mode, activity is detected that
wakes the USB interface up from suspend mode.
This interrupt is serviced by a specific vector, in order to wake up the ST7 from Halt
mode.
0: No End Suspend detected
1: End Suspend detected
This bit is set by hardware when the USB reset sequence is detected on the bus.
0: No USB reset signal detected
1: USB reset signal detected
Note: The DADDR, EP0RA, EP0RB, EP1RA, EP1RB, EP2RA and EP2RB
This bit is set by hardware when a low-speed SOF indication (keep-alive strobe) is
seen on the USB bus. It is also issued at the end of a resume sequence.
0: No SOF signal detected
1: SOF signal detected
registers are reset by a USB reset.
CTRM
Doc ID 7516 Rev 8
ERRM
Read.write
IOVRM
ESUSPM
RESETM
ST7263Bxx
SOFM
0