ST72321BJ6 STMicroelectronics, ST72321BJ6 Datasheet - Page 30

• Manufacturer Part Number: ST72321BJ6
• Description: 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72321BJ6

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

ST72321BRx, ST72321BARx ST72321BJx, ST72321BKx
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.2.2 Monitoring a Voltage on the EVD pin
This mode is selected by setting the AVDS bit in
the SICSR register.
The AVD circuitry can generate an interrupt when
the AVDIE bit of the SICSR register is set. This in-
terrupt is generated on the rising and falling edges
Figure 18. Using the Voltage Detector to Monitor the EVD pin (AVDS bit=1)
6.4.3 Low Power Modes
6.4.3.1 Interrupts
The AVD interrupt event generate an interrupt if
the corresponding Enable Control Bit (AVDIE) is
30/187
WAIT
HALT
AVDF
AVD INTERRUPT
REQUEST
IF AVDIE = 1
Mode
V
V
IT+(EVD)
IT-(EVD)
No effect on SI. AVD interrupts cause the
device to exit from Wait mode.
The SICSR register is frozen.
V
EVD
0
Description
INTERRUPT PROCESS
V
hyst
1
of the comparator output. This means it is generat-
ed when either one of these two events occur:
The EVD function is illustrated in
For more details, refer to the Electrical Character-
istics section.
set and the interrupt mask in the CC register is re-
set (RIM instruction).
AVD event
– V
– V
Interrupt Event
EVD
EVD
rises up to V
falls down to V
Event
AVDF
Flag
IT+(EVD)
IT-(EVD)
Control
Enable
AVDIE
Bit
INTERRUPT PROCESS
Figure
0
from
Wait
Exit
Yes
18.
from
Halt
Exit
No