ST72321BJ6 STMicroelectronics, ST72321BJ6 Datasheet - Page 101
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ST72321BJ6
Manufacturer Part Number
ST72321BJ6
Description
8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE
Manufacturer
STMicroelectronics
Datasheet
1.ST72321BJ6.pdf
(187 pages)
Specifications of ST72321BJ6
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4 Functional Description
The block diagram of the Serial Control Interface,
is shown in
isters:
– Two control registers (SCICR1 & SCICR2)
– A status register (SCISR)
– A baud rate register (SCIBRR)
– An extended prescaler receiver register (SCIER-
– An extended prescaler transmitter register (SCI-
Refer to the register descriptions in
for the definitions of each bit.
Figure 62. Word Length Programming
PR)
ETPR)
9-bit Word length (M bit is set)
Start
Figure 1.
Bit
8-bit Word length (M bit is reset)
Start
Bit
Bit0
Bit0
It contains six dedicated reg-
Bit1
Bit1
Data Frame
Idle Frame
Break Frame
Data Frame
Idle Frame
Break Frame
Bit2
Bit2
Section 0.1.7
Bit3
ST72321BRx, ST72321BARx ST72321BJx, ST72321BKx
Bit3
Bit4
Bit4
Bit5
Bit5
10.6.4.1 Serial Data Format
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 reg-
ister (see
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
Transmission and reception are driven by their
own baud rate generator.
Bit6
Bit6
Possible
Bit7
Parity
Figure
Bit7
Bit
Possible
Parity
Bit8
Bit
Stop
Bit
1.).
Stop
Bit
Extra
Start
Next
Start
Bit
Bit
‘1’
Extra
Next Data Frame
Next
Start
Start
Bit
Bit
‘1’
Start
Bit
Next Data Frame
Start
Bit
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