STM8SPLNB1 STMicroelectronics, STM8SPLNB1 Datasheet - Page 25
STM8SPLNB1
Manufacturer Part Number
STM8SPLNB1
Description
DiSEqC slave microcontroller for SaTCR based LNBs and switchers
Manufacturer
STMicroelectronics
Datasheet
1.STM8SPLNB1.pdf
(43 pages)
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STM8SPLNB1
4.3.4
Reset pin characteristics
Subject to general operating conditions for V
Table 26.
1. Data based on characterization results, not tested in production.
2. The R
The reset network shown in the following
resets. The user must ensure that the level on the NRST pin can go below the V
specified in the
account internally.
Figure 12. Recommended reset pin protection
R
Symbol
V
V
PU(RST)
IH(RST)
IL(RST)
PU
pull-up equivalent resistor is based on a resistive
RESET Input low level voltage
RESET Input high level voltage
RESET Pull-up resistor
RESET pin characteristics
Table 26.: RESET pin
Parameter
Doc ID 018831 Rev 3
(2)
characteristics. Otherwise the reset is not taken into
(1)
(1)
Figure 12.
Conditions
DD
and T
transistor.
protects the device against parasitic
A
unless otherwise specified.
0.7 x V
-0.3 V
Min
30
DD
Electrical characteristics
Typ
40
V
0.3 x V
DD
Max
60
+ 0.3
IL
max. level
DD
Unit
25/43
k
V
Ω