STM32F215RG STMicroelectronics, STM32F215RG Datasheet - Page 164

• Manufacturer Part Number: STM32F215RG
• Description: High-performance ARM Cortex-M3 MCU with 1 Mbyte Flash, 120 MHz CPU, ART Accelerator, HW crypto
• Manufacturer: STMicroelectronics

Specifications of STM32F215RG

• 10/100 Ethernet Mac With Dedicated Dma: supports IEEE 1588v2 hardware, MII/RMII

Revision history
164/168
Table 91.
22-Apr-2011
Date
Document revision history (continued)
(continued)
Revision
4
Updated t
APB1
TIMx connected to the APB2
Changed t
t
AC waveforms and measurement
Added
updated
Updated V
characteristics.
Updated
Updated R
Updated t
Updated
Modified FSMC_NOE waveform in
multiplexed SRAM/PSRAM/NOR read
FSMC_NEx/NADV/addresses/NWE/NOE/NWAIT of a half FSMC_CLK
period, changed t
AIV)
NWEH)
Synchronous multiplexed NOR/PSRAM read
Synchronous multiplexed PSRAM write
Synchronous non-multiplexed NOR/PSRAM read
Figure 61: Synchronous non-multiplexed PSRAM write
Changed t
t
modified t
Table
Updated R typical value in
characteristics.Updated note 2 in
Table
Modified t
waveforms for I/O space write
Modified FSMC_NCEx signal in
waveforms for read
write
memory read
common memory write
Specified Full speed (FS) mode for
peripheral-only connection in FS mode
host-only connection in FS
f(SCK)
d(CLKH-NOEH)
, t
Doc ID 17050 Rev 6
d(CLKH-NOEH)
access,
75.
71,
, and updated data latency from 1 to 0 in
domain. Modified t
to t
Table 53: USB OTG FS DC electrical characteristics
Table 54: USB OTG FS electrical
Table 62: ADC characteristics
Table 67: Embedded internal reference
Table
res(TIM)
f(SCL)
START
w(CLK)
h(NIOWR-D)
w(SCKH)
d(CLKH-NExH
DD
AIN
Figure 70: NAND controller waveforms for common
minimum value in
access, and
to t
equation. Updated
in
72,
in
minimum value in
in
d(CLKL-NOEH)
d(CLKH-NExH
Table 48: I2C characteristics
Table 65: TS
to t
to t
Table 46: Characteristics of TIMx connected to the
Table
access,
in
w(SCLH)
d(CLKL-NOEH)
) to t
Figure 67: PC Card/CompactFlash controller
access.
res(TIM)
73,
d(CLKL-NExH)
Figure 71: NAND controller waveforms for
Table 66: VBAT monitoring
mode.
Figure 69: NAND controller waveforms for
, t
Table
) to t
domain.
, t
Changes
access.
w(SCKL)
characteristics.
d(CLKH-NWEH)
Table 58: Ethernet DC electrical
and f
Figure 68: NAND controller
Table 64: DAC
Table
d(CLKL-NExH)
circuit.
Table
, and t
Figure 54: Asynchronous non-
74, and
Figure 86: USB OTG HS
STM32F215xx, STM32F217xx
EXT
to t
waveforms. Shifted end of
, t
and R
and
68,
timings,
72,
d(CLKH-AIV)
d(CLKH-NWEH)
Table 47: Characteristics of
w(SCLL)
characteristics.
Table
Table
Figure 87: USB OTG HS
Table
timings,
AIN
to t
, t
and
Figure 58:
d(CLKH-AIV)
Figure 60:
characteristics.
, t
d(CLKL-NWEH)
voltage.
equation.
69,
75.
timings, and
73,
r(SCK)
Figure 38: I2C bus
to t
Table
Figure 59:
Table
to t
d(CLKL-AIV)
timings,
to t
d(CLKL-
to t
70,
r(SCL)
and
74, and
, and
d(CLKL-
, and
,