EP2AGX260EF29I5 Altera Corporation, EP2AGX260EF29I5 Datasheet - Page 74

• Manufacturer Part Number: EP2AGX260EF29I5
• Description: IC ARRIA II GX FPGA 260K 780FBGA
• Manufacturer: Altera Corporation
• Series: Arria II GXr

Specifications of EP2AGX260EF29I5

• Number Of Logic Elements/cells: 244188
• Number Of Labs/clbs: 10260
• Total Ram Bits: 12038144
• Number Of I /o: 372
• Number Of Gates: -
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-BBGA
• Lead Free Status: Contains lead
• Rohs Status: RoHS non-compliant

1–66
Table 1–54. High-Speed I/O Specifications for Arria II GZ Devices
Table 1–55. DPA Lock Time Specifications for Arria II Devices
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
TCCS
Receiver
True differential I/O
standards - f
(data rate)
f
DPA run length
Soft-CDR PPM
tolerance
Sampling Window
(SW)
Notes to
(1) When J = 3 to 10, use the SERDES block.
(2) When J = 1 or 2, bypass the SERDES block.
(3) Clock Boost Factor (W) is the ratio between input data rate to the input clock rate.
(4) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional,
(5) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew
(6) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board
(7) This is achieved by using the LVDS and DPA clock network.
(8) If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
(9) This only applies to DPA and soft-CDR modes.
(10) This only applies to LVDS source synchronous mode.
SPI-4
Parallel Rapid I/O
HSDR
or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
margin, transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin.
skew margin, transmitter delay margin, and the receiver sampling margin to determine the maximum data rate supported.
Standard
(data rate)
Symbol
Table
HSDRDPA
1–54:
00000000001111111111
Table 1–55
SERDES factor J = 2,
SERDES factor J = 1,
uses an SDR register
uses DDR registers
Soft-CDR mode
Non-DPA mode
Training Pattern
SERDES factor
SERDES factor
LVDS_E_3R
Conditions
J = 3 to 10
J = 3 to 10
DPA mode
True LVDS
Emulated
00001111
10010000
lists DPA lock time specifications for Arria II GX and GZ devices.
Min
150
—
—
(4)
(4)
(4)
—
—
—
Transitions in One
Repetition of the
Training Pattern
Number of Data
C3, I3
Typ
—
—
—
—
—
—
—
—
—
2
2
4
(Note
(Note 1), (2), (10)
10000
1), (2),
1250
Max
100
250
300
300
(6)
(5)
(5)
(3)
Repetitions per
Chapter 1: Device Datasheet for Arria II Devices
Transitions
Min
150
(Part 1 of 2)
Number of
—
—
—
—
—
(4)
(4)
(4)
256 Data
128
128
64
(Part 3 of 3)
December 2011 Altera Corporation
C4, I4
Typ
(4)
—
—
—
—
—
—
—
—
—
640 data transitions
640 data transitions
640 data transitions
Switching Characteristics
10000
1250
Max
100
250
300
300
(6)
(5)
(5)
Maximum
± PPM
Mbps
Mbps
Mbps
Mbps
Unit
ps
ps
UI
ps