EP2AGX260EF29I5 Altera Corporation, EP2AGX260EF29I5 Datasheet - Page 54

• Manufacturer Part Number: EP2AGX260EF29I5
• Description: IC ARRIA II GX FPGA 260K 780FBGA
• Manufacturer: Altera Corporation
• Series: Arria II GXr

Specifications of EP2AGX260EF29I5

• Number Of Logic Elements/cells: 244188
• Number Of Labs/clbs: 10260
• Total Ram Bits: 12038144
• Number Of I /o: 372
• Number Of Gates: -
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-BBGA
• Lead Free Status: Contains lead
• Rohs Status: RoHS non-compliant

1–46
Table 1–40. Transceiver Block Jitter Specifications for Arria II GX Devices
Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
Sinusoidal jitter
tolerance at
3072 Mbps
Notes to
(1) Dedicated refclk pins are used to drive the input reference clocks. The jitter numbers are valid for the stated conditions only.
(2) The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification.
(3) The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.
(4) The jitter numbers for PCIe are compliant to the PCIe Base Specification 2.0.
(5) The jitter numbers for SRIO are compliant to the RapidIO Specification 1.3.
(6) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
(7) The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification.
(8) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications.
(9) Arria II PCIe receivers are compliant to this specification provided the VTX_CM-DC-ACTIVEIDLE-DELTA of the upstream transmitter is less than 50 mV.
(10) The jitter numbers for Serial Advanced Technology Attachment (SATA) are compliant to the Serial ATA Revision 3.0 Specification.
(11) The jitter numbers for Common Public Radio Interface (CPRI) are compliant to the CPRI Specification V3.0.
(12) The jitter numbers for Open Base Station Architecture Initiative (OBSAI) are compliant to the OBSAI RP3 Specification V4.1.
SONET/SDH Transmit Jitter Generation
Peak-to-peak jitter at
622.08 Mbps
RMS jitter at 622.08 Mbps
Peak-to-peak jitter at 2488.32
Mbps
RMS jitter at 2488.32 Mbps
SONET/SDH Receiver Jitter Tolerance
Jitter tolerance at 622.08 Mbps
Description
Symbol/
Table
Description
Symbol/
1–40:
Jitter frequency =
Jitter frequency =
1843.2 KHz to 20
Pattern = CJPAT
Pattern = CJPAT
Table 1–41
Arria II GZ devices.
Conditions
21.8 KHz
MHz
lists the transceiver jitter specifications for all supported protocols for
Jitter frequency = 0.03 KHz
Jitter frequency = 250 KHz
(3)
(3)
Min
Pattern = PRBS15
Pattern = PRBS15
Pattern = PRBS15
Pattern = PRBS15
Pattern = PRBS15
Pattern = PRBS15
Pattern = PRBS15
Jitter frequency =
Conditions
> 8.5
> 0.1
25 KHZ
Typ
I3
Max
Min
Typ
> 8.5
> 0.1
C4
Min
—
—
—
—
(Note
(Note 1)
Max
–C3 and –I3
Chapter 1: Device Datasheet for Arria II Devices
> 0.15
Typ
—
—
—
—
> 1.5
> 15
1),
Min
(Part 10 of 10)
(2)
Max
0.01
0.01
(Part 1 of 7)
0.1
0.1
December 2011 Altera Corporation
C5, I5
Typ
> 8.5
> 0.1
Max
Min
—
—
—
—
Switching Characteristics
–C4 and –I4
Min
> 0.15
Typ
> 1.5
—
—
—
—
> 15
Typ
> 8.5
> 0.1
C6
Max
0.01
0.01
0.1
0.1
Max
Unit
UI
UI
UI
UI
UI
UI
UI
Unit
UI
UI