PSMN1R2-25YL NXP Semiconductors, PSMN1R2-25YL Datasheet

PSMN1R2-25YL

Manufacturer Part Number
PSMN1R2-25YL
Description
Manufacturer
NXP Semiconductors
Datasheet

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1. Product profile
1.1 General description
1.2 Features and benefits
1.3 Applications
1.4 Quick reference data
Logic level N-channel MOSFET in LFPAK package qualified to 150 °C. This product is
designed and qualified for use in a wide range of industrial, communications and domestic
equipment.
Table 1.
Symbol Parameter
V
I
P
T
Avalanche ruggedness
E
Dynamic characteristics
Q
Q
D
j
DS
tot
DS(AL)S
GD
G(tot)
Advanced TrenchMOS provides low
RDSon and low gate charge
High efficiency gains in switching
power converters
DC-to-DC converters
Lithium-ion battery protection
Load switching
PSMN1R2-25YL
N-channel 25 V 1.2 mΩ logic level MOSFET in LFPAK
Rev. 01 — 25 June 2009
drain-source voltage T
drain current
total power
dissipation
junction temperature
non-repetitive
drain-source
avalanche energy
gate-drain charge
total gate charge
Quick reference
Conditions
T
see
T
V
I
R
V
V
see
D
j
mb
mb
GS
GS
DS
GS
≥ 25 °C; T
= 100 A; V
Figure 1
Figure 13
= 25 °C; V
= 25 °C; see
= 12 V; see
= 10 V; T
= 50 Ω; unclamped
= 4.5 V; I
j
sup
≤ 150 °C
D
j(init)
GS
= 25 A;
≤ 25 V;
Figure
Figure 2
= 10 V;
= 25 °C;
Improved mechanical and thermal
characteristics
LFPAK provides maximum power
density in a Power SO8 package
Motor control
Server power supplies
12;
[1]
Min
-
-
-
-55
-
-
-
Product data sheet
Typ
-
-
-
-
-
11.9
50.6
Max
25
100
121
150
677
-
-
Unit
V
A
W
°C
mJ
nC
nC

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PSMN1R2-25YL Summary of contents

Page 1

... PSMN1R2-25YL N-channel 25 V 1.2 mΩ logic level MOSFET in LFPAK Rev. 01 — 25 June 2009 1. Product profile 1.1 General description Logic level N-channel MOSFET in LFPAK package qualified to 150 °C. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. 1.2 Features and benefits ...

Page 2

... 100 °C; see °C; see j Simplified outline 1 SOT1023 (LFPAK2) Rev. 01 — 25 June 2009 PSMN1R2-25YL Min Typ Max - - 1.6 Figure 11 - 0.9 1.2 Figure 10 Graphic symbol D G mbb076 Version SOT1023 © NXP B.V. 2009. All rights reserved. ...

Page 3

... j(init Ω; unclamped R GS 003aad139 120 P der (%) 150 200 0 T (°C) mb Fig 2. Normalized total power dissipation as a function of mounting base temperature Rev. 01 — 25 June 2009 PSMN1R2-25YL Min Max - -20 20 [1] - 100 [1] - 100 Figure 3 - 815 - 121 -55 150 -55 150 - ...

Page 4

... Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN1R2-25YL_1 Product data sheet N-channel 25 V 1.2 mΩ logic level MOSFET in LFPAK / Conditions see Figure Rev. 01 — 25 June 2009 PSMN1R2-25YL 003aad199 10 us 100 100 (V) DS Min Typ Max - 0.4 1 ...

Page 5

... Figure 4 see Figure 12; see Figure see Figure MHz °C; see Figure 14 j Rev. 01 — 25 June 2009 PSMN1R2-25YL Min Typ Max Unit 1.3 1.7 2. 1.5 µ ...

Page 6

... 003aad128 12 R (on) DS (mΩ ° (V) GS Fig 6. Drain-source on-state resistance as a function of gate-source voltage; typical values Rev. 01 — 25 June 2009 PSMN1R2-25YL Min Typ Max Unit - 125 - 0.78 1 ...

Page 7

... Sub-threshold drain current as a function of gate-source voltage 003a a c337 10 R DS(on) (mΩ 120 180 T (°C) j Fig 10. Drain-source on-state resistance as a function of drain current; typical values Rev. 01 — 25 June 2009 PSMN1R2-25YL 003aab271 min typ max ( 003aad132 2.6 2.8 3 3 ...

Page 8

... T j 003aad134 (pF 12V 120 10 Q (nC) G Fig 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values Rev. 01 — 25 June 2009 PSMN1R2-25YL GS(pl) V GS(th GS1 GS2 G(tot) 003aaa508 003aad135 C ...

Page 9

... Fig 15. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values PSMN1R2-25YL_1 Product data sheet N-channel 25 V 1.2 mΩ logic level MOSFET in LFPAK 100 150 ° 0.2 0.4 0.6 0.8 Rev. 01 — 25 June 2009 PSMN1R2-25YL 003aad133 25 ° (V) SD © NXP B.V. 2009. All rights reserved ...

Page 10

... detail X 0 2.5 scale (1) (1) (1) ( 0.25 0.30 4.70 4.45 5.30 3.7 1.27 0.19 0.24 4.45 4.95 3.5 References JEDEC JEITA Rev. 01 — 25 June 2009 PSMN1R2-25YL (3× θ θ ° 6.2 1.3 0.85 8 0.25 0.1 ° 5.9 0.8 0.40 0 European Issue date projection 08-10-13 09-05-26 © NXP B.V. 2009. All rights reserved. ...

Page 11

... Revision history Table 7. Revision history Document ID Release date PSMN1R2-25YL_1 20090625 PSMN1R2-25YL_1 Product data sheet N-channel 25 V 1.2 mΩ logic level MOSFET in LFPAK Data sheet status Change notice Product data sheet - Rev. 01 — 25 June 2009 PSMN1R2-25YL Supersedes - © NXP B.V. 2009. All rights reserved ...

Page 12

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS — trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 25 June 2009 PSMN1R2-25YL © NXP B.V. 2009. All rights reserved ...

Page 13

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: PSMN1R2-25YL_1 All rights reserved. Date of release: 25 June 2009 ...

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