PMV45EN NXP Semiconductors, PMV45EN Datasheet

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology

PMV45EN

Manufacturer Part Number
PMV45EN
Description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology
Manufacturer
NXP Semiconductors
Datasheet

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1. Product profile
Table 1.
2. Pinning information
Table 2.
Symbol
V
I
V
Static characteristics
R
Pin
1
2
3
D
DS
GS
DSon
Symbol Description
G
S
D
Quick reference data
Pinning information
Parameter
drain-source voltage
drain current
gate-source voltage
drain-source on-state
resistance
1.1 General description
1.2 Features and benefits
1.3 Applications
1.4 Quick reference data
gate
source
drain
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications.
PMV45EN
N-channel TrenchMOS logic level FET
Rev. 2 — 7 November 2011
Logic-level compatible
Very fast switching
Battery management
Conditions
T
T
see
V
Figure
j
sp
GS
≥ 25 °C; T
= 25 °C; V
Figure 3
= 10 V; I
9; see
Simplified outline
j
D
≤ 150 °C
Figure 10
GS
= 2 A; T
SOT23 (TO-236AB)
= 10 V; see
1
j
= 25 °C; see
3
Figure
2
1;
Trench MOSFET technology
High-speed switching
Graphic symbol
Min
-
-
-20
-
mbb076
G
Product data sheet
Typ
-
-
-
35
D
S
Max
30
5.4
20
42
Unit
V
A
V
mΩ

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PMV45EN Summary of contents

Page 1

... PMV45EN N-channel TrenchMOS logic level FET Rev. 2 — 7 November 2011 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications. ...

Page 2

... Figure °C; see Figure °C sp ≤ 10 µ °C; pulsed All information provided in this document is subject to legal disclaimers. Rev. 2 — 7 November 2011 PMV45EN N-channel TrenchMOS logic level FET Version SOT23 [1] Min Max - kΩ -20 20 Figure ...

Page 3

... T (°C) sp Fig 2. Normalized total power dissipation as a function of solder point temperature DC 1 All information provided in this document is subject to legal disclaimers. Rev. 2 — 7 November 2011 PMV45EN N-channel TrenchMOS logic level FET 03aa17 50 100 150 T (°C) sp 03al02 μ s 100 μ s ...

Page 4

... Transient thermal impedance from junction to solder point as a function of pulse duration PMV45EN Product data sheet Conditions see Figure All information provided in this document is subject to legal disclaimers. Rev. 2 — 7 November 2011 PMV45EN N-channel TrenchMOS logic level FET Min Typ Max - - 60 03ak68 δ ...

Page 5

... Ω °C G(ext 1 °C; see Figure 12 All information provided in this document is subject to legal disclaimers. Rev. 2 — 7 November 2011 PMV45EN N-channel TrenchMOS logic level FET Min Typ Max 1 2.2 ...

Page 6

... Transfer characteristics: drain current as a function of gate-source voltage; typical values 2.5 V GS(th) (V) 2 max 1.5 typ min 1 0 Gate-source threshold voltage as a function of junction temperature PMV45EN 03ak72 150 ° (V) 03aa33 120 180 ( ° © NXP B.V. 2011. All rights reserved ...

Page 7

... I D (A) Fig 10. Normalized drain-source on-state resistance 03ak75 (nC) Fig 12. Source current as a function of source-drain All information provided in this document is subject to legal disclaimers. Rev. 2 — 7 November 2011 PMV45EN N-channel TrenchMOS logic level FET 1.8 a 1.2 0.6 0 − factor as a function of junction temperature ...

Page 8

... 3.0 1.4 2.5 1.9 0.95 2.8 1.2 2.1 REFERENCES JEDEC JEITA TO-236AB All information provided in this document is subject to legal disclaimers. Rev. 2 — 7 November 2011 PMV45EN N-channel TrenchMOS logic level FET detail 0.45 0.55 0.2 0.1 0.15 0.45 EUROPEAN PROJECTION SOT23 ...

Page 9

... All information provided in this document is subject to legal disclaimers. Rev. 2 — 7 November 2011 PMV45EN N-channel TrenchMOS logic level FET solder lands solder resist solder paste occupied area Dimensions in mm sot023_fr solder lands solder resist occupied area Dimensions in mm ...

Page 10

... NXP Semiconductors 10. Revision history Table 8. Revision history Document ID Release date PMV45EN v.2 20111107 • Modifications: The format of this document has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. ...

Page 11

... Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. All information provided in this document is subject to legal disclaimers. Rev. 2 — 7 November 2011 PMV45EN N-channel TrenchMOS logic level FET © NXP B.V. 2011. All rights reserved ...

Page 12

... TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 2 — 7 November 2011 PMV45EN N-channel TrenchMOS logic level FET © NXP B.V. 2011. All rights reserved ...

Page 13

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PMV45EN All rights reserved. Date of release: 7 November 2011 Document identifier: PMV45EN ...

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