JN5148 NXP Semiconductors, JN5148 Datasheet - Page 42

• Manufacturer Part Number: JN5148
• Description: The JN5148 is an ultra low power, high performance MCU combined with an IEEE802
• Manufacturer: NXP Semiconductors

The Tick Timer is clocked from a continuous 16MHz clock, which is fed to a 32-bit wide resettable up-counter, gated
by a signal from the mode control block. A match register allows comparison between the counter and a
programmed value. The match value, measured in 16MHz clock cycles is programmed through software, in the
range 0 to 0x0FFFFFFF. The output of the comparison can be used to generate an interrupt if the interrupt is
enabled and used in controlling the counter in the different modes. Upon configuring the timer mode, the counter is
also reset.
If the mode is programmed as single shot, the counter begins to count from zero until the match value is reached.
The match signal will be generated which will cause an interrupt if enabled, and the counter will stop counting. The
counter is restarted by reprogramming the mode.
If the mode is programmed as restartable, the operation of the counter is the same as for the single shot mode,
except that when the match value is reached the counter is reset and begins counting from zero. An interrupt will be
generated when the match value is reached if it is enabled.
Continuous mode operation is similar to restartable, except that when the match value is reached, the counter is not
reset but continues to count. An interrupt will be generated when the match value is reached if enabled.
11.3 Wakeup Timers
Two 32-bit wakeup timers are available in the JN5148 driven from the 32kHz internal clock. They may run during
sleep periods when the majority of the rest of the device is powered down, to time sleep periods or other long period
timings that may be required by the application. The wakeup timers do not run during deep sleep and may optionally
be disabled in sleep mode through software control. When a wakeup timer expires it typically generates an interrupt,
if the device is asleep then the interrupt may be used as an event to end the sleep period. See Section 21 for further
details on how they are used during sleep periods. Features include:
42
•
•
•
•
•
•
28-bit match value
Maskable timer interrupt
Single-shot, Restartable or Continuous modes of operation
35-bit down-counter
Optionally runs during sleep periods
Clocked by 32kHz system clock; either 32kHz RC oscillator, 32kHz XTAL oscillator or 32kHz clock input
SysClk
Run
&
Match Value
Counter
Control
Reset
Mode
JN-DS-JN5148-001 1v7
Figure 32: Tick Timer
Mode
=
Match
Enable
Int
&
© NXP Laboratories UK 2011
Tick Timer
Interrupt