TDF8599B NXP Semiconductors, TDF8599B Datasheet - Page 52

• Manufacturer Part Number: TDF8599B
• Description: The TDF8599B is a dual Bridge-Tied Load (BTL) car audio amplifier comprising anNDMOST-NDMOST output stage based on SOI BCDMOS technology
• Manufacturer: NXP Semiconductors

NXP Semiconductors
22. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. Overview of TDF8599B protection
Table 11. Available data on pins DIAG and CLIP . . . . . .18
Table 12. Interpretation of DC load detection bits . . . . . .20
Table 13. I
23. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. AD modulation . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Fig 11. BD modulation . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Fig 12. Master and slave operation with
Fig 13. Parallel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Fig 14. DC offset protection and diagnostic output . . . . .16
Fig 15. Diagnostic output for short circuit conditions . . . .18
Fig 16. DC load detection circuit . . . . . . . . . . . . . . . . . . .19
Fig 17. DC load detection procedure . . . . . . . . . . . . . . . .19
Fig 18. DC load detection limits . . . . . . . . . . . . . . . . . . . .19
Fig 19. Recommended start-up sequence with DC load
Fig 20. Start-up and shutdown timing in I
Fig 21. Start-up and shutdown timing in non-I
Fig 22. I
Fig 23. Data bits sent from Master microprocessor
Fig 24. I
TDF8599B_1
Product data sheet
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Heatsink up (top view) pin configuration
TDF8599BTH. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Clock frequency as a function of R
Master and slave configuration . . . . . . . . . . . . . . .8
Spread spectrum mode . . . . . . . . . . . . . . . . . . . . .9
Spread spectrum operation in Master mode . . . . .9
Phase lock operation . . . . . . . . . . . . . . . . . . . . . .10
AD/BD modulation switching circuit . . . . . . . . . . .12
shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
detection enabled. . . . . . . . . . . . . . . . . . . . . . . . .21
mode with DC load detection . . . . . . . . . . . . . . . .22
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
(Mmp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2
2
C-bus start and stop conditions. . . . . . . . . . . . .24
C-bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Quick reference data . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4
I
Non-I
Mode setting pin OSCIO . . . . . . . . . . . . . . . . . .7
Oscillator modes . . . . . . . . . . . . . . . . . . . . . . .10
Operation mode selection with the MOD pin . .11
Overview of protection types . . . . . . . . . . . . . .15
circuits and amplifier states . . . . . . . . . . . . . . .17
2
2
C-bus mode operation . . . . . . . . . . . . . . . . . . .7
C-bus write address selection using
2
C-bus mode operation . . . . . . . . . . . . . . .7
1
2
2
C-bus
osc
p phase
2
. . . . . . . . . .8
C-bus
Rev. 01 — 29 July 2009
I
2
C-bus controlled dual channel class-D power amplifier
Table 14. Instruction byte descriptions . . . . . . . . . . . . . . 25
Table 15. Phase shift bit settings . . . . . . . . . . . . . . . . . . 25
Table 16. Description of data bytes . . . . . . . . . . . . . . . . . 26
Table 17. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 18. Thermal characteristics . . . . . . . . . . . . . . . . . . 28
Table 19. Static characteristics . . . . . . . . . . . . . . . . . . . . 28
Table 20. Switching characteristics . . . . . . . . . . . . . . . . . 31
Table 21. Dynamic characteristics . . . . . . . . . . . . . . . . . 32
Table 22. Filter component values . . . . . . . . . . . . . . . . . 36
Table 23. SnPb eutectic process (from J-STD-020C) . . . 48
Table 24. Lead-free process (from J-STD-020C) . . . . . . 48
Table 25. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 26. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 50
Fig 25. I
Fig 26. P
Fig 27. P
Fig 28. P
Fig 29. P
Fig 30. THD + N as a function of output power with
Fig 31. THD + N as a function of output power with
Fig 32. THD + N as a function of output power with
Fig 33. THD + N as a function of output power with
Fig 34. THD + N as a function of frequency with a
Fig 35. THD + N as a function of frequency with a
Fig 36. THD + N as a function of frequency with a
Fig 37. Gain as a function of frequency. . . . . . . . . . . . . . 39
Fig 38. Output power as a function of supply voltage
Fig 39. Output power as a function of supply voltage
Fig 40. Channel separation as a function of frequency
THD = 0.5 % . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
THD = 10 %. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
THD = 0.5 % . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
THD = 10 %. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
a 2 W load; V
a 4 W load; V
a 2 W load; V
a 4 W load; V
2 W load, BD modulation; V
4 W load, BD modulation; V
2 W load, BD modulation; V
with a 2 W load . . . . . . . . . . . . . . . . . . . . . . . . . . 39
with a 4 W load . . . . . . . . . . . . . . . . . . . . . . . . . . 39
with 1 W output power, BD modulation . . . . . . . . 40
2
o
o
o
o
C-bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
pins MOD and ADS . . . . . . . . . . . . . . . . . . . . . 23
as a function of V
as a function of V
as a function of V
as a function of V
P
P
P
P
= 14.4 V. . . . . . . . . . . . . . . . . . . . 37
= 14.4 V. . . . . . . . . . . . . . . . . . . . 37
= 24 V . . . . . . . . . . . . . . . . . . . . . 38
= 24 V . . . . . . . . . . . . . . . . . . . . . 38
P
P
P
P
in stereo mode with
in stereo mode with
in parallel mode with
parallel mode with
TDF8599B
P
P
P
= 14.4 V . . . . . . . . 38
= 14.4 V . . . . . . . . 38
= 24 V . . . . . . . . . . 39
© NXP B.V. 2009. All rights reserved.
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