ADUC7023 Analog Devices, ADUC7023 Datasheet - Page 82

• Manufacturer Part Number: ADUC7023
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7023

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 20
• Adc # Channels: 12
• Other: PWM

ADuC7023
Table 99. IRQCLRE MMR Bit Designations
Bit
31 to
21
20
19
18
17
16
15 to
14
13
12 to
0
TIMERS
The ADuC7023 has three general-purpose timer/counters:
Timer0, Timer1, and Timer2 or Watchdog Timer.
These three timers in their normal mode of operation can be
either free-running or periodic.
In free-running mode, the counter decreases from the
maximum value until zero scale and starts again at the
minimum value. (It also increases from the minimum value
until full scale and starts again at the maximum value.)
In periodic mode, the counter decrements/increments from the
value in the load register (TxLD MMR) until zero/full scale and
starts again at the value stored in the load register.
The timer interval is calculated as follows:
The value of a counter can be read at any time by accessing its
value register (TxVAL). When a timer is being clocked from a
clock other than core clock, an incorrect value may be read (due
to asynchronous clock system). In this configuration, TxVAL
should always be read twice. If the two readings are different, it
should be read a third time to get the correct value.
Timers are started by writing in the control register of the
corresponding timer (TxCON).
In normal mode, an IRQ is generated each time the value of the
counter reaches zero when counting down. It is also generated
each time the counter value reaches full scale when counting
Interval
Name
Reserved
PLA1CLRI
IRQ3CLRI
IRQ2CLRI
PLA0CLRI
IRQ1CLRI
Reserved
IRQ0CLRI
Reserved
=
(
TxD
Source
Description
These bits are reserved and should not be
written to.
A 1 must be written to this bit in the PLA
IRQ1 interrupt service routine to clear an
edge triggered PLA IRQ1 interrupt.
A 1 must be written to this bit in the
external IRQ3 interrupt service routine to
clear an edge triggered IRQ3 interrupt.
A 1 must be written to this bit in the
external IRQ2 interrupt service routine to
clear an edge triggered IRQ2 interrupt.
A 1 must be written to this bit in the PLA
IRQ0 interrupt service routine to clear an
edge triggered PLA IRQ0 interrupt.
A 1 must be written to this bit in the
external IRQ1 interrupt service routine to
clear an edge triggered IRQ1 interrupt.
These bits are reserved and should not be
written to.
A 1 must be written to this bit in the
external IRQ0 interrupt service routine to
clear an edge triggered IRQ0 interrupt.
These bits are reserved and should not be
written to.
)
×
Prescaler
Clock
Rev. B | Page 82 of 96
up. An IRQ can be cleared by writing any value to clear the
register of that particular timer (TxCLRI).
When using an asynchronous clock-to-clock timer, the
interrupt in the timer block can take more time to clear
than the time it takes for the code in the interrupt routine to
execute. Ensure that the interrupt signal is cleared before
leaving the interrupt service routine. This can be done by
checking the IRQSTA MMR.
Timer0 (RTOS Timer)
Timer0 is a general-purpose, 16-bit timer (count-down) with a
programmable prescaler (see Figure 42). The prescaler source is
the core clock frequency (HCLK) and can be scaled by factors
of 1, 16, or 256.
Timer0 can be used to start ADC conversions as shown in the
block diagram in Figure 42.
OSCILLATOR
The Timer0 interface consists of four MMRs: T0LD, T0VAL,
T0CON, and T0CLRI.
T0LD Register
Name:
Address:
Default value:
Access:
T0LD is a 16-bit load register.
T0VAL Register
Name:
Address:
Default Value:
Access:
T0VAL is a 16-bit read-only register representing the current
state of the counter.
32.768kHz
UCLK
HCLK
Figure 42. Timer0 Block Diagram
T0LD
0xFFFF0300
0x0000
Read/write
T0VAL
0xFFFF0304
0xFFFF
Read
/1, 16, OR 256
PRESCALER
COUNTER
TIMER0
VALUE
DOWN
16-BIT
16-BIT
LOAD
TIMER0 IRQ
ADC CONVERSION