ADUC7023 Analog Devices, ADUC7023 Datasheet - Page 41

• Manufacturer Part Number: ADUC7023
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7023

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 20
• Adc # Channels: 12
• Other: PWM

REMAP Register
Name:
Address:
Default value:
Access:
Table 35. REMAP MMR Bit Designations
Bit
7 to 5
4
3
2 to 1
0
Reset Operation
There are four kinds of reset: external, power-on, watchdog
expiration, and software force. The RSTSTA register indicates
the source of the last reset, and RSTCLR allows clearing of the
RSTSTA register. These registers can be used during a reset
exception service routine to identify the source of the reset. If
RSTSTA is null, the reset is external.
The RSTCFG register allows different peripherals to retain their
state after a watchdog or software reset.
RSTSTA Register
Name:
Address:
Default value:
Access:
Name
JTAFO
Remap
RSTSTA
0x01
Read/write
0xFFFF0230
REMAP
0xFFFF0220
0x00
Read/write
Description
Reserved.
Read-only bit. Indicates the size of the
Flash/EE memory available. If this bit is set,
only 32 kB of Flash/EE memory is available.
Read-only bit. Indicates the size of the
SRAM memory available. If this bit is set,
only 4 kB of SRAM is available.
Read only bits. See the P0.0/BM
description for further details.
If = [00], then P0.1/P0.2/P0.3 are
configured as JTAG pins.
If = [1x], then P0.1/P0.2/P0.3 are
configured as GPIO pins.
These bits are configured by the kernel
after any reset sequence and depend on
the state of P0.0 during the last reset
sequence.
Remap bit.
This bit is set by the user to remap the
SRAM to Address 0x00000000.
This bit is cleared automatically after reset
to remap the Flash/EE memory to Address
0x00000000.
Rev. B | Page 41 of 96
Table 36. RSTSTA MMR Bit Designations
Bit
7 to 3
2
1
0
RSTCLR Register
Name:
Address:
Default value:
Access:
Function:
RSTCFG Register
Name:
Address:
Default value:
Access:
Table 37. RSTCFG MMR Bit Designations
Bit
7 to 3
2
1
0
Description
Reserved. Always set to 0.
This bit is set to 1 to configure the DAC outputs to retain
their state after a watchdog or software reset.
This bit is cleared for the DAC pins and registers to
return to their default state.
Reserved. Always set to 0.
This bit is set to 1 to configure the GPIO pins to retain
their state after a watchdog or software reset.
This bit is cleared for the GPIO pins and registers to
return to their default state.
Description
Reserved.
Software reset.
This bit is set by the user to force a software reset.
This bit is cleared by setting the corresponding bit
in RSTCLR.
Watchdog timeout.
This bit is set automatically when a watchdog
timeout occurs.
This bit is cleared by setting the corresponding bit
in RSTCLR.
Power-on reset.
This bit is set automatically when a power-on reset
occurs.
This bit is cleared by setting the corresponding bit
in RSTCLR.
RSTCLR
0xFFFF0234
0x00
Write
Note that to clear the RSTSTA register, users
must write the Value 0x07 to the RSTCLR
register.
RSTCFG
0xFFFF024C
0x00
Read/write
ADuC7023