ADUC824 Analog Devices, ADUC824 Datasheet - Page 63

• Manufacturer Part Number: ADUC824
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 8kB Flash + 16/24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC824

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 256Bytes
• Gpio Pins: 34
• Adc # Channels: 4

In either implementation, Port 0 (P0) serves as a multiplexed
address/data bus. It emits the low byte of the data pointer (DPL) as
an address, which is latched by a pulse of ALE prior to data being
placed on the bus by the ADuC824 (write operation) or the
SRAM (read operation). Port 2 (P2) provides the data pointer
page byte (DPP) to be latched by ALE, followed by the data
pointer high byte (DPH). If no latch is connected to P2, DPP is
ignored by the SRAM, and the 8051 standard of 64 Kbyte external
data memory access is maintained.
Detailed timing diagrams of external program and data memory
read and write access can be found in the timing specification
sections of this data sheet.
Power-On Reset Operation
External POR (power-on reset) circuitry must be implemented to
drive the RESET pin of the ADuC824. The circuit must hold
the RESET pin asserted (high) whenever the power supply
(DV
2.5 V for at least 10 ms before the RESET signal is deasserted
(low) by which time the power supply must have reached at
least a 2.7 V level. The external POR circuit must be opera-
tional down to 1.2 V or less. The timing diagram of Figure 47
illustrates this functionality under three separate events: power-
up, brownout, and power-down. Notice that when RESET is
asserted (high) it tracks the voltage on DV
The best way to implement an external POR function to meet
the above requirements involves the use of a dedicated POR chip,
such as the ADM809/ADM810 SOT-23 packaged PORs from
Analog Devices. Recommended connection diagrams for both
active-high ADM810 and active-low ADM809 PORs are shown
in Figure 48 and Figure 49 respectively.
RESET
DV
DD
DD
) is below 2.5 V. Furthermore, V
1.2V MAX
2.5V MIN
ADuC824
ALE
WR
RD
P2
P0
10ms
MIN
LATCH
LATCH
10ms
MIN
DD
DD
OE
WE
D0–D7
(DATA)
A0–A7
A8–A15
A16–A23
must remain above
.
SRAM
1.2V MAX
Some active-low POR chips, such as the ADM809 can be used with
a manual push-button as an additional reset source as illustrated
by the dashed line connection in Figure 49.
Power Supplies
The ADuC824’s operational power supply voltage range is 2.7 V
to 5.25 V. Although the guaranteed data sheet specifications are
given only for power supplies within 2.7 V to 3.6 V or +5% of
the nominal 5 V level, the chip will function equally well at any
power supply level between 2.7 V and 5.25 V.
Separate analog and digital power supply pins (AV
respectively) allow AV
signals often present on the system DVDD line. In this mode the
part can also operate with split supplies; that is, using different
voltage supply levels for each supply. For example, this means that
the system can be designed to operate with a DV
of 3 V while the AV
A typical split supply configuration is show in Figure 50.
1k
DIGITAL SUPPLY
POWER SUPPLY
POWER SUPPLY
+
–
0.1 F
OPTIONAL
MANUAL RESET
PUSH-BUTTON
(ACTIVE LOW)
(ACTIVE HIGH)
10 F
DD
POR
POR
DD
level can be at 5 V or vice versa if required.
to be kept relatively free of noisy digital
20
34
48
21
35
47
DV
DGND
DD
ADuC824
20
34
48
15
20
34
48
15
AV
AGND
DV
RESET
DD
DV
RESET
DD
10 F
ADuC824
ANALOG SUPPLY
DD
ADuC824
5
6
ADuC824
0.1 F
DD
DD
voltage level
+
–
and DV
DD