ADUC824 Analog Devices, ADUC824 Datasheet - Page 57

• Manufacturer Part Number: ADUC824
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 8kB Flash + 16/24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC824

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 256Bytes
• Gpio Pins: 34
• Adc # Channels: 4

UART SERIAL INTERFACE
The serial port is full duplex, meaning it can transmit and receive
simultaneously. It is also receive-buffered, meaning it can com-
mence reception of a second byte before a previously received
byte has been read from the receive register. However, if the first
byte still has not been read by the time reception of the second
byte is complete, the first byte will be lost. The physical interface
to the serial data network is via Pins RXD(P3.0) and TXD(P3.1)
SCON
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
S
M
0
Name
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
S
M
1
UART Serial Port Control Register
98H
00H
Yes
Description
UART Serial Mode Select Bits
These bits select the Serial Port operating mode as follows:
SM0
0
0
1
1
Multiprocessor Communication Enable Bit
Enables multiprocessor communication in Modes 2 and 3. In Mode 0, SM2 should be cleared.
In Mode 1, if SM2 is set, RI will not be activated if a valid stop bit was not received. If SM2 is
cleared, RI will be set as soon as the byte of data has been received. In Modes 2 or 3, if SM2 is
set, RI will not be activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI will
be set as soon as the byte of data has been received.
Serial Port Receive Enable Bit
Set by user software to enable serial port reception.
Cleared by user software to disable serial port reception.
Serial Port Transmit (Bit 9)
The data loaded into TB8 will be the ninth data bit that will be transmitted in Modes 2 and 3.
Serial Port Receiver Bit 9
The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1 the stop bit is
latched into RB8.
Serial Port Transmit Interrupt Flag
Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in
Modes 1, 2, and 3.
TI must be cleared by user software.
Serial Port Receiver Interrupt Flag
Set by hardware at the end of the eighth bit in mode 0, or halfway through the stop bit in
Modes 1, 2, and 3.
RI must be cleared by software.
S
M
2
Table XXVII. SCON SFR Bit Designations
SM1
0
1
0
1
R
E
N
Selected Operating Mode
Mode 0: Shift Register, fixed baud rate (Core_Clk/2)
Mode 1: 8-bit UART, variable baud rate
Mode 2: 9-bit UART, fixed baud rate (Core_Clk/64) or (Core_Clk/32)
Mode 3: 9-bit UART, variable baud rate
while the SFR interface to the UART is comprised of the fol-
lowing registers.
SBUF
The serial port receive and transmit registers are both accessed
through the SBUF SFR (SFR address = 99 hex). Writing to
SBUF loads the transmit register and reading SBUF accesses a
physically separate receive register.
T
B
8
R
B
8
T
I
ADuC824
R
I