ADUC824 Analog Devices, ADUC824 Datasheet
ADUC824
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ADUC824 Summary of contents
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... I/O ports (SPI, UART, and I On-chip factory firmware supports in-circuit serial download and debug modes (via UART), as well as single-pin emulation mode via the EA pin. A functional block diagram of the ADuC824 is shown above with a more detailed block diagram shown in Figure 12. ...
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... Sigma-Delta Modulator ................................................... 35 Digital Filter .................................................................... 35 ADC Chopping ............................................................... 36 Calibration ...................................................................... 37 NONVOLATILE FLASH/EE MEMORY ........................... 37 Flash/EE Memory Overview ............................................. 37 Flash/EE Memory and the ADuC824 ............................... 37 ADuC824 Flash/EE Memory Reliability ........................... 37 Using the Flash/EE Program Memory .............................. 38 Flash/EE Program Memory Security ................................ 39 Using the Flash/EE Data Memory .................................... 39 USER INTERFACE TO OTHER ON-CHIP ADuC824 PERIPHERALS ...
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... Bits min Bits p-p typ ppm of FSR max LSB typ µV/°C typ LSB typ ppm/°C typ dBs min dBs min dBs min Bits LSB typ LSB max mV max % max % typ µs typ nVs typ ADuC824 to T MIN MAX ...
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... ANALOG (DAC) OUTPUTS Voltage Range Resistive Load Capacitive Load Output Impedance I SINK TEMPERATURE SENSOR Accuracy Thermal Impedance (θ ADuC824BS Test Conditions/Comments 1.25 ± 1% Initial Tolerance @ 25° 100 2.5 ± 1% Initial Tolerance @ 25° ± 100 External Reference Voltage = 2.5 V RN2, RN1, RN0 of ADC0CON Set to ± ...
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... All Digital Inputs ADuC824 Unit nA typ nA typ % typ %/°C typ µA typ % typ ppm/°C typ ppm/°C typ µA/V typ µA/V typ V max min V max V max V min V min/V max V min/V max ...
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... FLASH/EE MEMORY RELIABILITY CHARACTERISTICS 15 Endurance 16 Data Retention POWER REQUIREMENTS Power Supply Voltages Nominal Operation Nominal Operation Nominal Operation Nominal Operation DD ADuC824BS Test Conditions/Comments 2 2 SOURCE 2 SOURCE 0 mA, SCLOCK, SDATA/MOSI V max SINK 0 mA, P1 ...
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... V, Core CLK = 1.57 MHz µA typ DD = 5.25 V, Core CLK = 12.58 MHz µA typ DD = 5.25 V, Osc Osc. Off )/125, where: REF ADuC824 Unit mA max mA max µA max mA max mA max µA max mA max µA typ mA typ mA typ µA max µA max µ ...
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... C LOAD 4 ADuC824 internal PLL locks onto a multiple (384 times) the external crystal frequency of 32.768 kHz to provide a Stable 12.583 MHz internal clock for the system. The core can operate at this frequency binary submultiple called Core_Clk, selected via the PLLCON SFR. 5 This number is measured at the default Core_Clk operating frequency of 1.57 MHz. ...
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... LHLL PLPH AVLL LLPL t LLIV t PLIV t PLAZ t LLAX PCL INSTRUCTION (OUT) t AVIV PCH ADuC824 Variable Core_Clk Min Max Unit 2t – CORE t – CORE t – CORE 4t – 100 ns CORE t – CORE 3t – ...
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... ADuC824 Parameter EXTERNAL DATA MEMORY READ CYCLE RD Pulsewidth t RLRH t Address Valid after ALE Low AVLL t Address Hold after ALE Low LLAX RD Low to Valid Data In t RLDV Data and Address Hold after RD t RHDX Data Float after RD t RHDZ t ALE Low to Valid Data In ...
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... LLWL WLWH t AVWL t QVWX t LLAX t AVLL t QVWH A0–A7 DATA A16–A23 A8–A15 ADuC824 Variable Core_Clk Min Max Unit 6t – 100 ns CORE t – CORE t – CORE 3t – CORE CORE 4t – 130 ...
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... ADuC824 Parameter UART TIMING (Shift Register Mode) t Serial Port Clock Cycle Time XLXL t Output Data Setup to Clock QVXH t Input Data Setup to Clock DVXH t Input Data Hold after Clock XHDX t Output Data Hold after Clock XHQX ALE (O) TXD (OUTPUT CLOCK) RXD (OUTPUT DATA) ...
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... MSB LSB t t DHD t t SHD SUP L Max Unit µs µs µs µs µs 0.9 µs µs µs 300 ns 300 ACK MSB t DSU F t DHD t RSU REPEATED START ADuC824 Figure ...
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... ADuC824 Parameter SPI MASTER MODE TIMING (CPHA = 1) t SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge DSU t Data Input Hold Time after SCLOCK Edge DHD t Data Output Fall Time ...
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... SCLOCK (CPOL = 1) t DOSU MOSI MISO MSB IN t DSU Min 100 100 DAV MSB BITS 6–1 BITS 6–1 t DHD ADuC824 Typ Max Unit 630 ns 630 150 ...
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... ADuC824 Parameter SPI SLAVE MODE TIMING (CPHA = SCLOCK Edge SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge DSU t Data Input Hold Time after SCLOCK Edge ...
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... SCLOCK (CPOL = 1) t DOSS MISO MOSI t DSU Min 0 100 100 DAV BITS 6–1 MSB BITS 6–1 MSB IN t DHD ADuC824 Typ Max Unit ns 330 ns 330 ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADuC824 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Interrupt 1, programmable edge-or level-triggered Interrupt input, which can be programmed to one of two priority levels. This pin can also be used as a gate control input to Timer1. 20, 34 Digital supply 21, 35, 47 DGND S Digital ground, ground reference point for the digital circuitry PIN FUNCTION DESCRIPTIONS ADuC824 ...
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... In the following descriptions, SET implies a Logic 1 state and CLEARED implies a Logic 0 state unless otherwise stated the following descriptions, SET and CLEARED also imply that the bit is set or automatically cleared by the ADuC824 hardware unless otherwise stated. 3. User software should not write 1s to reserved or unimplemented bits as they may be used in future products. ...
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... FLASH/EE WATCHDOG 8K 8 TIMER 8052 PROGRAM FLASH/EE POWER SUPPLY MCU MONITOR CORE DEBUGGER SYNCHRONOUS SERIAL INTERFACE 2 (SPI ADuC824 12-BIT DAC BUF 16-BIT T1 23 COUNTER 1 T2 TIMERS 2 T2EX TIME INTERVAL INT0 COUNTER 18 INT1 19 PROG. CLOCK ...
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... ADuC824 MEMORY ORGANIZATION As with all 8051-compatible devices, the ADuC824 has sepa- rate address spaces for Program and Data memory as shown in Figure 13 and Figure 14. If the user applies power or resets the device while the EA pin is pulled low, the part will execute code from the external program space, otherwise the part defaults to code execution from its internal 8 Kbyte Flash/EE program memory ...
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... The SFR space is mapped to the upper 128 bytes of internal data memory space and accessed by direct addressing only. It provides an interface between the CPU and all on-chip peripherals. A block diagram showing the programming model of the ADuC824 via the SFR area is shown in Figure 16. A complete SFR map is shown in Figure 17. ...
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... ADuC824 SPECIAL FUNCTION REGISTERS All registers, except the program counter and the four general- purpose register banks, reside in the SFR area. The SFR registers include control, configuration, and data registers that provide an interface between the CPU and all on-chip peripherals. ISPI ...
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... Table III. ADCSTAT SFR Bit Designations . REF ADuC824 Current Source Control Register. Allows user control of the various on-chip current source options. these three 8-bit registers. Auxiliary ADC 16-bit conversion result held in these two 8-bit registers. Primary ADC 24-bit Offset Calibration Coefficient held in these three 8-bit registers ...
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... ADuC824 ADCMODE (ADC Mode Register) Used to control the operational mode of both ADCs. SFR Address D1H Power-On Default Value 00H Bit Addressable No — — Bit Name Description 7 — Reserved for Future Use 6 — Reserved for Future Use 5 ADC0EN Primary ADC Enable Set by the user to enable the Primary ADC and place it in the mode selected in MD2– ...
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... RN0 Selected Primary ADC Input Range (V ± ± ± ± 160 ± 320 ± 640 ± 1. ± 2. ADuC824 1.25 V). REF = 2.5 V) REF ...
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... ADuC824 ADC1CON (Auxiliary ADC Control Register) Used to configure the Auxiliary ADC for channel selection, external Ref enable and unipolar or bipolar coding. It should be noted that the Auxiliary ADC only operates on a fixed input range of ± V SFR Address D3H Power-On Default Value 00H ...
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... I N Table VIII. ICON SFR Bit Designations High Data Byte Middle Data Byte Low Data Byte All Three registers All Three registers High Data Byte Low Data Byte Both Registers Both Registers ADuC824 DBH DAH D9H ...
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... ADuC824 OF0H/OF0M/OF0L (Primary ADC Offset Calibration Registers ) These three 8-bit registers hold the 24-bit offset calibration coefficient for the Primary ADC. These registers are configured at power- on with a factory default value of 800000Hex. However, these bytes will be automatically overwritten if an internal or system zero-scale calibration is initiated by the user via MD2– ...
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... PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION Overview The ADuC824 incorporates two independent sigma-delta ADCs (Primary and Auxiliary) with on-chip digital filtering intended for the measurement of wide dynamic range, low frequency signals, such as those in weigh-scale, strain-gauge, pressure trans- ducer or temperature measurement applications. ...
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... V reference). The single-ended inputs can be driven from AIN3, AIN4, or AIN5 pins or directly from the on-chip temperature sensor voltage. A block diagram of the Auxiliary ADC is shown in Figure 19. DIFFERENTIAL REFERENCE TO THE ADuC824 IS DIFFERENTIAL AND FACILITATES RATIOMETRIC SIGMA-DELTA ADC OPERATION. THE EXTERNAL THE SIGMA-DELTA VIA THE XREF1 BIT IN ADC1CON ...
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... The absolute input voltage range on the primary ADC is restricted to between AGND + 100 mV to AVDD – 100 mV. Care must be taken in setting up the common-mode voltage and input voltage range so that these limits are not exceeded, otherwise there will be a degradation in linearity performance. ADuC824 320 mV 640 mV 1.28 V 3.50 4 ...
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... For example, if AIN(–) is 2.5 V and the primary ADC is config- ured for an analog input range mV, the input voltage range on the AIN(+) input AIN(–) is 2.5 V and the ADuC824 is configured for an analog input range of 1.28 V, the analog input range on the AIN(+) input is 1. 3.78 V (i.e., 2.5 V ± 1.28 V). ...
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... Sigma-Delta Modulator A sigma-delta ADC generally consists of two main blocks, an analog modulator and a digital filter. In the case of the ADuC824 ADCs, the analog modulators consist of a difference amplifier, an integrator block, a comparator, and a feedback DAC as illus- trated in Figure 21. ...
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... The chopping scheme incorporated in the ADuC824 ADC results in excellent dc offset and offset drift specifications and is extremely beneficial in applications where drift, noise rejection, and optimum EMI rejection are important factors. 30 ...
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... TECHNOLOGY Overall, Flash/EE memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit programma- bility, high density, and low cost. Incorporated in the ADuC824, Flash/EE memory technology allows the user to update program code space in-circuit, without the need to replace one-time programmable (OTP) devices at remote operating nodes ...
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... Using the Flash/EE Program Memory The 8 Kbyte Flash/EE Program Memory array is mapped into the lower 8 Kbytes of the 64 Kbytes program space addressable by the ADuC824, and is used to hold user code in typical applications. The program memory Flash/EE memory arrays can be pro- grammed in one of two modes, namely: ...
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... Signature/ID 00H Program Code Byte Program Data Byte Read Code Byte As with other ADuC824 user-peripheral circuits, the interface to Read Data Byte this memory space is via a group of registers mapped in the SFR Program Security space. A group of four data registers (EDATA1–4) are used to Modes hold 4-byte page data just accessed ...
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... Table XIII. It should be noted that a given mode of operation is initiated as soon as the command word is written to the ECON SFR. The core microcontroller operation on the ADuC824 is idled until the requested Program/Read or Erase mode is completed. In practice, this means that even though the Flash/EE memory ...
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... The following section gives a brief overview of the various peripher- als also available on-chip. A summary of the SFRs used to control and configure these peripherals is also given. DAC The ADuC824 incorporates a 12-bit, voltage output DAC on-chip. It has a rail-to-rail voltage output buffer capable of driving DACCON DAC Control Register ...
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... ADuC824 ON-CHIP PLL The ADuC824 is intended for use with a 32.768 kHz watch crys- tal. A PLL locks onto a multiple (384) of this to provide a stable 12.582912 MHz clock for the system. The core can operate at this frequency or at binary submultiples allow power saving in cases where maximum core performance is not ...
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... IEIP2 SFR description under Interrupt System later in this data sheet.) If the ADuC824 is in power-down mode, again with TIC interrupt enabled, the TII bit will wake up the device and resume code execution by vectoring directly to the TIC interrupt service vector address at 0053 hex ...
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... ADuC824 TIMECON TIC Control Register SFR Address A1H Power-On Default Value 00H Bit Addressable No — — Bit Name Description 7 — Reserved for Future Use 6 — Reserved for Future Use. For future product code compatibility this bit should be written as a ‘1.’ ...
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... HOUR Hours Time Register Function This register is incremented in 1 hour intervals once TCEN in TIMECON is active. The HOUR SFR counts from before rolling over to 0. SFR Address A5H Power-On Default Value 00H Bit Addressable No Valid Value decimal ADuC824 ...
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... ADuC824 WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC824 enters an erroneous state, possibly due to a programming error, electrical noise, or RFI. The Watchdog function can be disabled by clearing the WDE (Watchdog Enable) bit in the Watchdog Control (WDCON) SFR. When enabled ...
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... POWER SUPPLY MONITOR As its name suggests, the Power Supply Monitor, once enabled, monitors both supplies (AVDD or DVDD) on the ADuC824. It will indicate when any of the supply pins drop below one of four user-selectable voltage trip points from 2. 4.63 V. For correct operation of the Power Supply Monitor function, AV must be equal to or greater than 2 ...
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... SPI peripheral. This line is active low. Data is only received or transmitted in slave mode when the SS pin is low, allowing the ADuC824 to be used in single master, multislave SPI configurations. If CPHA = 1 then the SS input may be permanently pulled low. With CPHA = 0 then the ...
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... SPIDAT register. The SCLOCK bit rate is determined by SPR0 and SPR1 in SPICON. It should also be noted that the SS pin is not used in master mode. If the ADuC824 needs to assert the SS pin on an external slave device, a Port digital output pin should be used. ...
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... ADuC824 2 I C-COMPATIBLE INTERFACE The ADuC824 supports a 2-wire serial interface mode which compatible. The I C-compatible interface shares its pins with the on-chip SPI interface and therefore the user can only enable one or the other interface at any given time (see SPE in ...
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... SFR bit definitions. Parallel I/O Ports 0–3 The ADuC824 uses four input/output ports to exchange data with external devices. In addition to performing general-purpose I/O, some ports are capable of external memory operations; others are multiplexed with an alternate function for the peripheral features on the device ...
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... ADuC824 User configuration and control of all Timer operating modes is achieved via three SFRs namely: TMOD, TCON: Control and configuration for Timers 0 and 1. T2CON: Control and configuration for Timer 2. TMOD Timer/Counter 0 and 1 Mode Register SFR Address 89H Power-On Default Value 00H Bit Addressable ...
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... TH0 and TL0 Timer 0 high byte and low byte. SFR Address = 8Chex, 8Ahex respectively. TH1 and TL1 Timer 1 high byte and low byte. SFR Address = 8Dhex, 8Bhex respectively Table XXIV. TCON SFR Bit Designations ADuC824 ...
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... ADuC824 TIMER/COUNTER 0 AND 1 OPERATING MODES The following paragraphs describe the operating modes for timer/ counters 0 and 1. Unless otherwise noted, assume that these modes of operation are the same for timer 0 as for timer 1. Mode 0 (13-Bit Timer/Counter) Mode 0 configures an 8-bit timer/counter with a divide-by-32 pre- scaler ...
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... Timer 2, data high byte and low byte. SFR Address = CDhex, CChex respectively. RCAP2H and RCAP2L Timer 2, Capture/Reload byte and low byte. SFR Address = CBhex, CAhex respectively Table XXV. T2CON SFR Bit Designations ADuC824 ...
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... ADuC824 Timer/Counter 2 Operating Modes The following paragraphs describe the operating modes for timer/ counter 2. The operating modes are selected by bits in the T2CON SFR as shown in Table XXVI. Table XXVI. TIMECON SFR Bit Designations RCLK (or) TCLK CAP2 TR2 ...
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... Table XXVII. SCON SFR Bit Designations SM1 Selected Operating Mode 0 Mode 0: Shift Register, fixed baud rate (Core_Clk/2) 1 Mode 1: 8-bit UART, variable baud rate 0 Mode 2: 9-bit UART, fixed baud rate (Core_Clk/64) or (Core_Clk/32) 1 Mode 3: 9-bit UART, variable baud rate ADuC824 ...
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... ADuC824 Mode 0: 8-Bit Shift Register Mode Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmitted or received. Transmission is initiated by any instruction that writes to SBUF. ...
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... CONTROL TIMER 2 OVERFLOW TL2 TH2 (8-BITS) (8-BITS) TR2 RELOAD RCAP2L RCAP2H EXF TIMER 2 2 INTERRUPT CONTROL EXEN2 ADuC824 RCAP2H RCAP2L Actual % Value Value Baud Error –1 (FFh) –20 (ECh) 19661 2.4 –1 (FFh) –41 (D7h) 9591 0.1 –1 (FFh) –164 (5Ch) 2398 0.1 – ...
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... ADuC824 INTERRUPT SYSTEM The ADuC824 provides a total of twelve interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three Interrupt-related SFRs. IE: Interrupt Enable Register. IP: Interrupt Priority Register. IEIP2: Secondary Interrupt Priority-Interrupt Register. IE Interrupt Enable Register ...
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... IE SFR. This is done to ensure that the interrupt will always be responded watch dog timeout occurs. The watchdog will only produce an interrupt if the watchdog timeout is greater than zero. ADuC824 ...
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... Single Pin Emulation Mode section of this data sheet. External program memory (if used) must be connected to the ADuC824 as illustrated in Figure 44. Note that 16 I/O lines (Ports 0 and 2) are dedicated to bus functions during external program memory fetches. Port 0 (P0) serves as a multiplexed address/data bus. It emits the low byte of the program counter (PCL address, and then goes into a float state awaiting the arrival of the code byte from the program memory ...
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... It emits the low byte of the data pointer (DPL address, which is latched by a pulse of ALE prior to data being placed on the bus by the ADuC824 (write operation) or the SRAM (read operation). Port 2 (P2) provides the data pointer page byte (DPP latched by ALE, followed by the data pointer high byte (DPH) ...
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... Port pins retain their logic levels in this mode, but the DAC output goes to a high-impedance state (three-state) while ALE and PSEN outputs are held low. During full power-down mode the ADuC824 consumes a total of 5 µA typically. There are five ways of terminating power-down mode Asserting the RESET Pin (#15) 0 ...
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... ADuC824’s digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than the ADuC824 input pins. A value of 100 Ω or 200 Ω is usually sufficient to prevent high-speed signals from coupling capacitively into the ADuC824 and affecting the accuracy of ADC conversions. ...
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... The only hardware concern is then one of determining if adequate space is available for the emulator pod to fit into the system enclosure. Typical System Configuration A typical ADuC824 configuration is shown in Figure 53. It sum- marizes some of the hardware considerations discussed in the previous paragraphs. DOWNLOAD/DEBUG ENABLE JUMPER ...
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... QUICKSTART DEVELOPMENT SYSTEM The QuickStart Development System is a full featured, low cost development tool suite supporting the ADuC824. The system consists of the following PC-based (Windows-compatible) hard- ware and software development tools. Hardware: ADuC824 Evaluation Board, Plug-In Power Supply and Serial Port Cable ...
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... ADuC824 CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Revision History Location 5/02—Data Sheet changed from REV REV. B. Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3/01—Data Sheet changed from REV REV. A. ...