ADM1066 Analog Devices, ADM1066 Datasheet - Page 28

• Manufacturer Part Number: ADM1066
• Manufacturer: Analog Devices

Specifications of ADM1066

• # Supplies Monitored: 12
• Volt Monitoring Accuracy: 1%
• # Output Drivers: 10
• Fet Drive/enable Output: Both
• Voltage Readback: 12-bit ADC
• Supply Adj/margining: 12-bit ADC+6 DACs
• Package: 40 ld LFCSP ,48 ld TQFP

ADM1066
SMBus PROTOCOLS FOR RAM AND EEPROM
The ADM1066 contains volatile registers (RAM) and nonvolatile
registers (EEPROM). User RAM occupies Address 0x00 to
Address 0xDF; the EEPROM occupies Address 0xF800 to
Address 0xFBFF.
Data can be written to and read from both the RAM and the
EEPROM as single data bytes. Data can be written only to
unprogrammed EEPROM locations. To write new data to a
programmed location, the location contents must first be erased.
EEPROM erasure cannot be done at the byte level. The EEPROM
is arranged as 32 pages of 32 bytes each, and an entire page
must be erased.
Page erasure is enabled by setting Bit 2 in the UPDCFG register
(Address 0x90) to 1. If this bit is not set, page erasure cannot
occur, even if the command byte (0xFE) is programmed across
the SMBus.
WRITE OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The following abbreviations
are used in Figure 39 to Figure 47:
•
•
•
•
•
•
S = Start
P = Stop
R = Read
W = Write
A = Acknowledge
A = No acknowledge
(CONTINUED)
(CONTINUED)
SDA
SCL
SDA
SCL
START BY
SDA
SCL
MASTER
P
t
1
BUF
0
S
1
D7
1
D6
SLAVE ADDRESS
1
t
LO W
t
HD; STA
FRAME 1
t
D5
HD; DAT
0
D4
1
DATA BYTE
t
FRAME 3
R
A1
D3
Figure 37. General SMBus Read Timing Diagram
A0
D2
Figure 38. Serial Bus Timing Diagram
t
R/W
SU; DAT
ACK. BY
D1
SLAVE
Rev. E | Page 28 of 32
9
D0
ACK. BY
MASTER
t
HI G H
t
F
1
9
D7
D6
1
The ADM1066 uses the following SMBus write protocols.
Send Byte
In a send byte operation, the master device sends a single
command byte to a slave device, as follows:
1.
2.
3.
4.
5.
6.
In the ADM1066, the send byte protocol is used for two
purposes:
•
•
D5
D7
D4
D6
S
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts an acknowledge (ACK)
on SDA.
The master sends a command code.
The slave asserts an ACK on SDA.
The master asserts a stop condition on SDA, and the
transaction ends.
To write a register address to the RAM for a subsequent
single byte read from the same address, or for a block read
or block write starting at that address, as shown in Figure 39.
To erase a page of EEPROM memory. EEPROM memory
can be written to only if it is unprogrammed. Before writing
to one or more EEPROM memory locations that are already
programmed, the page(s) containing those locations must
first be erased. EEPROM memory is erased by writing a
command byte.
DATA BYTE
FRAME 2
t
D5
D3
SU; STA
Figure 39. Setting a RAM Address for Subsequent Read
S
1
t
D2
D4
HD; STA
DATA BYTE
FRAME N
ADDRESS
SLAVE
D1
D3
2
ACK. BY
MASTER
D0
D2
W
9
D1
t
SU; STO
A
3
D0
NO ACK.
(0x00 TO 0xDF)
ADDRESS
9
RAM
4
P
MASTER
STOP
BY
A
5
P
6