ADP5585 Analog Devices, ADP5585 Datasheet - Page 13

• Manufacturer Part Number: ADP5585
• Description: Keypad Decoder and I/O Expansion
• Manufacturer: Analog Devices

Specifications of ADP5585

• Vin Range: 1.8 to 3.0V
• Application: Mobil I-0 Exp-Keybd Cont,Mobil I-O Expander
• Qwerty Keypad: Yes
• Other Functions: I2C I/O & register
• Function Flag: Mobil I-O
• Package: 16-Lead WLCSP

Data Sheet
R3_EXTEND_CFG[1:0]
LOGIC_SEL[2:0]
(R1) LA
(R2)
(R3)
RESET_TRIG_TIME[2:0]
RESET1_EVENT_A[7:0]
RESET1_EVENT_B[7:0]
RESET1_EVENT_C[7:0]
RESET2_EVENT_A[7:0]
RESET2_EVENT_B[7:0]
FF_SET
FF_CLR
LA_INV
LB_INV
LC_INV
LY_INV
LOGIC_INT_LEVEL
LOGIC_EVENT_EN
LB
LC
LOGIC BLOCK
D
LC
SET
CLR
Figure 18. Logic Block Overview
LB
LA
R3_EXTEND_CFG[1:0] = 01
Q
GENERATOR
LC
LC
EVENT/INT
LB
LB
LA
LA
PWM_OFFT_HIGH_BYTE[7:0]
PWM_OFFT_LOW_BYTE[7:0]
PWM_ONT_HIGH_BYTE[7:0]
LOGIC
PWM_ONT_LOW_BYTE[7:0]
LC_INV
LB_INV
0
1
0
1
LA_INV
0
1
SEL
SEL
SEL
OUT
OUT
OUT
LY (R0)
LOGIC EVENT
KEY EVENT
GPI EVENT
IN_LC
I
IN_LB
2
IN_LA
C BUSY
EVENT_INT
LOGIC_INT
PWM_IN_AND
(C3) PWM_IN
PWM_MODE
PWM_EN
IN_LA
IN_LB
IN_LC
IN_LA
IN_LB
IN_LC
IN_LA
IN_LB
IN_LC
IN_LA
IN_LB
IN_LC
UPDATE
FF_CLR
FIFO
XOR
AND
OR
OVRFLOW_INT
OFF TIME[15:0]
ON TIME[15:0]
FF_SET
Figure 20. PWM Block Diagram
EC[4:0]
FIFO
0
1
Figure 19. Logic Block
Rev. A | Page 13 of 36
SEL
OUT
XOR
AND
OR
0
1
0
1
0
1
D
SEL
SEL
SEL
SET
CLR
GENERATOR
OUT
OUT
OUT
Q
PWM BLOCK
The ADP5585 features a PWM generator whose output can be
configured to drive out on the R3 I/O pin. PWM on/off times
are programmed via four 8-bit registers (see Figure 20). Each
bit of the on or off time represents 1 μs. The highest frequency
obtainable from the PWM is performed by setting the least
significant bit of both the on and off time bit patterns, resulting
in a 500 kHz signal with a 50% duty cycle.
The PWM block provides support for continuous PWM mode
as well as a one-shot mode (see Table 59). Additionally, an
external signal can be AND’ e d with the internal PWM signal.
This option can be selected by writing a 1 to PWM_IN_AND
(PWM_CFG[2]). The input to the external AND is the C3 I/O
pin. C3 should be set to GPI. Note that the debounce for C3
results in a delay of the AND’ing, and can be turned on or off
using Register 0x21.
Newly programmed values are not latched until the final byte,
PWM_ONT_HIGH_BYTE (Register 0x32, Bits[7:0]), is written.
PWM
AND
OR
XOR
FF
IN_LA
IN_LB
IN_LC
GND
AND
AND
XOR
OR
FF
LOGIC_SEL[2:0]
000
001
010
011
100
101
110
111
SEL[2:0]
0
1
MUX
SEL
OUT
OUT
(R3)
PWM_OUT
LY
LY
0
1
LY_INV
SEL
OUT
LY
ADP5585