ADP5585 Analog Devices, ADP5585 Datasheet
ADP5585
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ADP5585 Summary of contents
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... Smart phones, remote controls, and cameras Healthcare, industrial, and instrumentation GENERAL DESCRIPTION The ADP5585 input/output port expander with a built in keypad matrix decoder, programmable logic, reset generator, and PWM generator. Input/output expander ICs are used in portable devices (phones, remote controls, and cameras) and nonportable applications (healthcare, industrial, and instrumentation) ...
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... ADP5585 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Diagram ........................................................................... 4 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Theory of Operation ........................................................................ 7 Device Enable................................................................................ 8 Device Overview .......................................................................... 8 REVISION HISTORY 10/11—Rev. Sp0 to Rev. A Added 16-Lead LFCSP_WQ Package..............................Universal Changes to Features Section............................................................ 1 Added Figure 4 ...
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... GPIOs active simultaneously V Sink current = 10 mA, all GPIOs active OL2 simultaneously V Source current = OH-Leak OL3 SINK OL4 SINK V OH-Leak OSC FREQ Rev Page ADP5585 Min Typ Max Unit 1.65 3.6 V 1.2 1.3 V 1.4 1 μ μ μ μ ...
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... ADP5585 Parameter TIMING SPECIFICATIONS 2 Delay from UVLO/Reset Inactive Access SCL Clock Frequency SCL High Time SCL Low Time Data Setup Time Data Hold Time Setup Time for Repeated Start Hold Time for Start/Repeated Start Bus Free Time for Stop and Start Condition ...
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... JA ), using the following soldered in a printed circuit board (PCB) for surface-mount JA packages. Table 3. Thermal Resistance 16-Ball WLCSP Maximum Power Dissipation 16-Lead LFCSP Maximum Power Dissipation ESD CAUTION Rev Page ADP5585 θ Unit JA 62 °C 67.154 °C ...
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... GPIO 10 (GPIO Alternate Function: PWM_IN). This pin functions as Column 3 when used as a keypad. GPIO 11 (GPIO Alternate Function: RESET2). This pin functions as Column 4 when used as a keypad. Input Reset Signal. To expand the keypad matrix, select the ADP5585ACBZ-01-R7 or the ADP5585ACPZ-01-R7 device model for this pin to function as GPIO 6/Row 5. ...
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... GPI SCAN (RST/R5) GPIO 6 AND (C0) GPIO 7 DECODE (C1) GPIO 8 (C2) GPIO 9 (C3) GPIO 10 (C4) GPIO 11 (R1) LA (R2) LB LOGIC (R3) LC (R0) LY PWM_IN (C3) PWM PWM_OUT (R3) RESET1 (R4) RESET1 GEN RST (R5) RESET2 (C4) RESET2 GEN Figure 5. Internal Block Diagram Rev Page GND INT FIFO UPDATE REGISTERS ADP5585 ...
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... I device status and pending interrupts can be flagged to an external processor by using the INT pin. The ADP5585 is offered with three feature sets. Table 5 lists the options that are available for each model of the ADP5585. Table 5. Matrix Options by Device Model ...
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... Before going into detail on the various ADP5585 blocks important to understand the function of the event FIFO. The ADP5585 features an event FIFO that can record as many as 16 events. By default, the FIFO primarily records key events, such as key press and key release. However possible to configure the general-purpose input (GPI) and logic activity to generate event information on the FIFO as well ...
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... ADP5585 VDD KEY SCAN CONTROL × 3 KEYPAD MATRIX Figure 9. Simplified Key Scan Block Figure 9 shows a simplified representation of the key scan block using three row and three column pins connected to a small 3 × 3, nine-switch keypad matrix. When the key scanner is idle, the row pins are pulled high and the column pins are driven low ...
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... When the key scanner completes scanning, it normally detects Key 1 to Key 5 as being pressed; however, this unique condition is decoded by the ADP5585, and Key Event 31 is assigned to it eight more key event assignments are possible, allowing the keypad size to extend up to 30. However, if one of the extended keys is pressed, none of the keys on that row is detectable ...
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... I/O structure. See the Detailed Register Descriptions section for GPO configuration and usage. LOGIC BLOCKS Several of the ADP5585 input/output lines can be used as inputs and outputs for implementing some common logic functions. The R1, R2, and R3 input/output pins can be used as inputs, and the R0 input/output pin can be used as an output for the logic block ...
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... PWM_OFFT_HIGH_BYTE[7:0] PWM_ONT_LOW_BYTE[7:0] PWM_ONT_HIGH_BYTE[7:0] PWM BLOCK The ADP5585 features a PWM generator whose output can be configured to drive out on the R3 I/O pin. PWM on/off times are programmed via four 8-bit registers (see Figure 20). Each bit of the on or off time represents 1 μs. The highest frequency obtainable from the PWM is performed by setting the least significant bit of both the on and off time bit patterns, resulting in a 500 kHz signal with a 50% duty cycle ...
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... ADP5585 RESET BLOCKS ADP5585 features two reset blocks that can generate reset con- ditions if certain events are detected simultaneously three reset trigger events can be programmed for RESET1 two reset trigger events can be programmed for RESET2. The event scan control blocks monitor whether these events are present for the duration of RESET_TRIG_TIME[2:0] (Register 0x2E, Bits[4:2]) ...
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... C cycles required The ADP5585 pulls the data line low after every byte, and a stop condition completes the sequence. Figure 25 shows a typical byte read sequence for reading inter- nal registers. The cycle begins with a start condition followed ...
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... ADP5585 acknowledges the address byte by pulling the data line low. The address of the register from which data read is sent next. The ADP5585 acknowledges the register pointer byte by pulling the data line low. A start condition is repeated, followed by the 7-bit device address (0x34 for all models except the ...
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... DEB_DIS DEB_DIS GPO_4_ GPO_3_ GPO_2_ DATA DATA DATA GPO_10_ GPO_9_ GPO_8_ DATA DATA DATA GPO_4_ GPO_3_ GPO_2_ OUT_MODE OUT_MODE OUT_MODE ADP5585 Bit 0 EVENT_INT GPI_1_INT GPI_7_INT GPI_1_STAT GPI_7_STAT GPI_1_ INT_LEVEL GPI_7_ INT_LEVEL GPI_1_ EVENT_EN GPI_7_ EVENT_EN GPI_1_ INT_EN GPI_7_ INT_EN GPI_1_ DEB_DIS ...
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... ADP5585 Reg Reg 1 Add Name R/W Bit 7 0x26 GPO_OUT_ R/W MODE_B 0x27 GPIO_ R/W DIRECTION_A 0x28 GPIO_ R/W DIRECTION_B 0x29 RESET1_EVENT_A R/W RESET1_ EVENT_ A_LEVEL 0x2A RESET1_EVENT_B R/W RESET1_ EVENT_ B_LEVEL 0x2B RESET1_EVENT_C R/W RESET1_ EVENT_ C_LEVEL 0x2C RESET2_EVENT_A R/W RESET2_ EVENT_ A_LEVEL 0x2D RESET2_EVENT_B R/W RESET2_ EVENT_ B_LEVEL 0x2E ...
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... For GPI and logic events from Event 37 to Event 48, use the following settings GPI/logic is active GPI/logic is inactive. Active and inactive states for Event 37 to Event 48 are programmable. Contains the event identifier for the pin. Refer to Table 11. Rev Page ADP5585 ...
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... ADP5585 Table 11. Event Decoding Event No. Meaning 0 No event 1 Key 1 (R0, C0) 2 Key 2 (R0, C1) 3 Key 3 (R0, C2) 4 Key 4 (R0, C3) 5 Key 5 (R0, C4) 6 Key 6 (R1, C0) 7 Key 7 (R1, C1) 8 Key 8 (R1, C2) 9 Key 9 (R1, C3) 10 Key 10 (R1, C4) 11 Key 11 (R2, C0) ...
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... Read only Read only Access Read only Read only Access Read only Read only Access Read only Read only Rev Page ADP5585 Description Refer to Table 10. Refer to Table 10. Description Refer to Table 10. Refer to Table 10. Description Refer to Table 10. Refer to Table 10. Description Refer to Table 10. ...
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... ADP5585 FIFO_13 Register 0x0F Table 23. FIFO_13 Bit Descriptions Bit(s) Bit Name 7 EVENT13_STATE EVENT13_IDENTIFIER[6:0] FIFO_14 Register 0x10 Table 24. FIFO_14 Bit Descriptions Bit(s) Bit Name 7 EVENT14_STATE EVENT14_IDENTIFIER[6:0] FIFO_15 Register 0x11 Table 25. FIFO_15 Bit Descriptions Bit(s) Bit Name 7 EVENT15_STATE EVENT15_IDENTIFIER[6:0] FIFO_16 Register 0x12 Table 26 ...
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... Rev Page ADP5585 ...
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... ADP5585 Bit(s) Bit Name Access R1_PULL_CFG Read/write R0_PULL_CFG Read/write RPULL_CONFIG_B Register 0x18 Table 32. RPULL_CONFIG_B Bit Descriptions Bit(s) Bit Name Access N R5_PULL_CFG Read/write R4_PULL_CFG Read/write RPULL_CONFIG_C Register 0x19 Table 33. RPULL_CONFIG_C Bit Descriptions Bit(s) Bit Name Access ...
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... GPI events from GPI allow GPI 3 activity to generate events on the FIFO 0 = disable GPI events from GPI allow GPI 2 activity to generate events on the FIFO 0 = disable GPI events from GPI allow GPI 1 activity to generate events on the FIFO Rev Page ADP5585 ...
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... ADP5585 GPI_EVENT_EN_B Register 0x1E Table 38. GPI_EVENT_EN_B Bit Descriptions Bit(s) Bit Name N/A 4 GPI_11_EVENT_EN 3 GPI_10_EVENT_EN 2 GPI_9_EVENT_EN 1 GPI_8_EVENT_EN 0 GPI_7_EVENT_EN 1 GPIs in this mode are considered FIFO events and can be used for unlock purposes. GPI activity in this mode cause EVENT_INT interrupts. GPIs in this mode do not generate GPI_INT interrupts ...
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... GPI debounce disabled on GPI 7. Access Description Reserved. Read/write 0 = sets output low sets output high. Read/write 0 = sets output low sets output high. Read/write 0 = sets output low sets output high. Read/write 0 = sets output low sets output high. Rev Page ADP5585 ...
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... ADP5585 Bit(s) Bit Name 1 GPO_2_DATA 0 GPO_1_DATA GPO_DATA_OUT_B Register 0x24 Table 44. GPO_DATA_OUT_B Bit Descriptions Bit(s) Bit Name N/A 4 GPO_11_DATA 3 GPO_10_DATA 2 GPO_9_DATA 1 GPO_8_DATA 0 GPO_7_DATA GPO_OUT_MODE_A Register 0x25 Table 45. Register 0x25, GPO_OUT_MODE_A Bit Descriptions Bit(s) Bit Name N/A 5 GPO_6_OUT_MODE 4 GPO_5_OUT_MODE 3 GPO_4_OUT_MODE 2 GPO_3_ OUT_MODE ...
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... Defines an event that can be used to generate the RESET1 signal three events can be defined for generating the RESET1 signal, using RESET1_EVENT_A[6:0], RESET1_EVENT_B[6:0], and RESET1_EVENT_C[6:0]. If one of the registers is 0, that register is not used for reset generation. All reset events must be detected at the same time to trigger the reset. Rev Page ADP5585 ...
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... ADP5585 RESET1_EVENT_B Register 0x2A Table 50. RESET1_EVENT_B Bit Descriptions Bit(s) Bit Name 7 RESET1_EVENT_B_LEVEL RESET1_EVENT_B[6:0] RESET1_EVENT_C Register 0x2B Table 51. RESET1_EVENT_C Bit Descriptions Bit(s) Bit Name 7 RESET1_EVENT_C_LEVEL RESET1_EVENT_C[6:0] RESET2_EVENT_A Register 0x2C Table 52. RESET2_EVENT_A Bit Descriptions Bit(s) Bit Name 7 RESET2_EVENT_A_LEVEL RESET2_EVENT_A[6:0] RESET2_EVENT_B Register 0x2D Table 53 ...
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... Read/write Defines PWM mode continuous executes one PWM period, then sets PWM_EN to 0. Read/write Enable PWM generator. Rev Page Description Lower eight bits of PWM off time. Description Upper eight bits of PWM off time. Description Lower eight bits of PWM on time. ADP5585 ...
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... ADP5585 LOGIC_CFG Register 0x34 Table 60. LOGIC_CFG Bit Descriptions Bit(s) Bit Name Access 7 N/A 6 LY_INV Read/write 5 LC_INV Read/write 4 LB_INV R/W 3 LA_INV R LOGIC_SEL[2:0] R/W LOGIC_FF_CFG Register 0x35 Table 61. LOGIC_FF_CFG Bit Descriptions Bit(s) Bit Name Access N/A Read/write 1 FF_SET Read/write 0 FF_CLR Read/write LOGIC_INT_EVENT_EN Register 0x36 Table 62 ...
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... Read/write remains configured as GPIO 11 reconfigured as RESET2 output. Rev Page ADP5585 Table 66 for alternate configuration, RESET1). Table 66 for alternate configuration, LY). for alternate configuration, RESET2). ...
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... INT pin remains asserted if an interrupt is pending INT pin deasserts for 50 μs and reasserts if an interrupt is pending. R/W Configure the response ADP5585 has to the RST pin ADP5585 resets if RST is low ADP5585 does not reset if RST is low. Access Description Reserved. Read/write 0 = Logic 1 interrupt is disabled. ...
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... Figure 27. Typical Application Schematic Rev Page VDD SDA SCL RST VDD ADP5585 UVLO OSCILLATOR 2 POR I C INTERFACE KEY SCAN AND DECODE GPI SCAN AND DECODE LOGIC I/O CONFIG PWM REGISTERS RESET1 GEN RESET2 GEN GND ADP5585 INT ...
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... Temperature Range ADP5585ACBZ-00-R7 −40°C to +85°C ADP5585ACBZ-01-R7 −40°C to +85°C ADP5585ACBZ-02-R7 −40°C to +85°C ADP5585ACPZ-00-R7 −40°C to +85°C ADP5585ACPZ-01-R7 −40°C to +85°C ADP5585ACPZ-03-R7 −40°C to +85°C ADP5585CP-EVALZ RoHS Compliant Part refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ...