AD9761 Analog Devices, AD9761 Datasheet - Page 6

• Manufacturer Part Number: AD9761
• Description: 10-Bit, Complete, 40 MSPS, dual Transmit D/A Converter
• Manufacturer: Analog Devices

Specifications of AD9761

• Resolution (bits): 10bit
• Dac Update Rate: 40MSPS
• Dac Settling Time: 35ns
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

Pin No.
1
2–9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
AD9761
Mnemonic
DB9
DB8–DB1
DB0
CLOCK
WRITE
SELECT
DVDD
DCOM
COMP3
QOUTA
QOUTB
REFLO
REFIO
FSADJ
COMP2
AVDD
ACOM
IOUTB
IOUTA
COMP1
RESET/SLEEP
Description
Most Significant Data Bit (MSB).
Data Bits 1–8.
Least Significant Data Bit (LSB).
Clock Input. Both DACs’ outputs updated on positive edge of clock and digital filters read respective
input registers.
Write Input. DAC input registers latched on positive edge of write.
Select Input. Select high routes input data to I DAC; select low routes data to Q DAC.
Digital Supply Voltage (2.7 V to 5.5 V).
Digital Common.
Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.
Q DAC Current Output. Full-scale current when all data bits are 1s.
Q DAC Complementary Current Output. Full-scale current when all data bits are 0s.
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.2 V
reference output when internal reference activated. Requires 0.1 µF capacitor to ACOM when internal
reference activated.
Full-Scale Current Output Adjust. Resistance to ACOM sets full-scale output current.
Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance.
Analog Supply Voltage (3 V to 5.5 V).
Analog Common.
I DAC Complementary Current Output. Full-scale current when all data bits are 0s.
I DAC Current Output. Full-scale current when all data bits are 1s.
Internal Bias Node for Switch Driver Circuitry. Decouple to AGND with 0.1 µF capacitor.
Power-Down Control Input if Asserted for Four Clock Cycles or Longer. Reset control input if
asserted for less than four clock cycles. Active high. Connect to DCOM if not used. Refer to RESET/
SLEEP Mode Operation section.
PIN FUNCTION DESCRIPTIONS
(MSB) DB9
(LSB) DB0
SELECT
CLOCK
WRITE
DVDD
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
PIN CONFIGURATION
10
12
13
14
11
1
2
3
4
5
6
7
8
9
(Not to Scale)
TOP VIEW
AD9761
–6–
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RESET/SLEEP
COMP1
IOUTA
IOUTB
ACOM
AVDD
COMP2
FSADJ
REFIO
REFLO
QOUTB
QOUTA
COMP3
DCOM
REV. C