AD9761 Analog Devices, AD9761 Datasheet - Page 3

• Manufacturer Part Number: AD9761
• Description: 10-Bit, Complete, 40 MSPS, dual Transmit D/A Converter
• Manufacturer: Analog Devices

Specifications of AD9761

• Resolution (bits): 10bit
• Dac Update Rate: 40MSPS
• Dac Settling Time: 35ns
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

DYNAMIC SPECIFICATIONS
Parameter
DYNAMIC PERFORMANCE
AC LINEARITY TO NYQUIST
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Parameter
DIGITAL INPUTS
*t
Specifications subject to change without notice.
REV. C
CINV
Total Harmonic Distortion (THD)
Maximum Output Update Rate
Output Settling Time (t
Output Propagation Delay (t
Glitch Impulse
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
Signal-to-Noise and Distortion (SINAD)
Effective Number of Bits (ENOBs)
Spurious-Free Dynamic Range (SFDR)
Channel Isolation
Logic 1 Voltage @ DVDD = 5 V
Logic 1 Voltage @ DVDD = 3 V
Logic 0 Voltage @ DVDD = 5 V
Logic 0 Voltage @ DVDD = 3 V
Logic 1 Current
Logic 0 Current
Input Capacitance
Input Setup Time (t
Input Hold Time (t
CLOCK High
CLOCK Low
Invalid CLOCK/WRITE Window (t
T
T
f
f
f
f
OUT
OUT
OUT
OUT
is an invalid window of 4 ns duration beginning 1 ns after the rising edge of WRITE in which the rising edge of CLOCK must not occur.
A
MIN
= 25°C
= 1 MHz; CLOCK = 40 MSPS
= 1 MHz; CLOCK = 40 MSPS
= 1 MHz; CLOCK = 40 MSPS; 10 MHz Span
= 8 MHz; CLOCK = 40 MSPS; 10 MHz Span
to T
MAX
DB9–DB0
SELECT
INPUTS
CLOCK
H
WRITE
S
)
)
DAC
ST
to 0.025%)
PD
)
t
S
t
CINV
H
(T
)*
MIN
(T
50  Doubly Terminated, unless otherwise noted.)
t
I DATA
MIN
CINV
to T
to T
MAX
, AVDD = 5 V, DVDD = 5 V, I
MAX
Figure 1.Timing Diagram
, AVDD = 5 V, DVDD = 5 V, I
Q DATA
Min
40
56
9.0
59
Min
3.5
2.4
–10
–10
1
–3–
OUTFS
NOTE: WRITE AND CLOCK CAN BE
TIED TOGETHER. FOR TYPICAL EXAMPLES,
REFER TO DIGITAL INPUTS AND INTERLEAVED
INTERFACE CONSIDERATION SECTION.
OUTFS
Typ
35
55
5
2.5
2.5
59
9.5
–68
–67
68
90
Typ
5
3
0
0
5
3
2
5
5
= 10 mA unless otherwise noted.)
= 10 mA, Differential Transformer Coupled Output,
Max
–58
–53
Max
1.3
0.9
+10
+10
5
Unit
MSPS
ns
Input Clock Cycles
pV-s
ns
ns
dB
Bits
dB
dB
dB
dBc
Unit
V
V
V
V
µA
µA
pF
ns
ns
ns
ns
ns
AD9761