AD9778 Analog Devices, AD9778 Datasheet - Page 37

no-image

AD9778

Manufacturer Part Number
AD9778
Description
Dual 14-Bit, 1 GSPS, Digital-to-Analog Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD9778

Resolution (bits)
14bit
Dac Update Rate
1GSPS
Dac Settling Time
n/a
Max Pos Supply (v)
+3.47V
Single-supply
No
Dac Type
Current Out
Dac Input Format
Par

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9778ABSVZ
Manufacturer:
Analog Devices Inc
Quantity:
135
Part Number:
AD9778ABSVZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD9778ABSVZ
Manufacturer:
AD
Quantity:
1 000
Part Number:
AD9778ABSVZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD9778ABSVZRL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD9778BSVZ
Manufacturer:
ADI
Quantity:
184
Part Number:
AD9778BSVZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD9778BSVZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD9778BSVZRL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Table 18. VCO Frequency Range vs. PLL Band Select Value
PLL Band Select
111111 (63)
111110 (62)
111101 (61)
111100 (60)
111011 (59)
111010 58)
111001 (57)
111000 (56)
110111 (55)
110110 (54)
110101 (53)
110100 (52)
110011 (51)
110010 (50)
110001 (49)
110000 (48)
101111 (47)
101110 (46)
101101 (45)
101100 (44)
101011 (43)
101010 (42)
101001 (41)
101000 (40)
100111 (39)
100110 (38)
100101 (37)
100100 (36)
100011 (35)
100010 (34)
100001 (33)
100000 (32)
011111 (31)
011110 (30)
011101 (29)
011100 (28)
011011 (27)
011010 (26)
011001 (25)
011000 (24)
010111 (23)
010110 (22)
010101 (21)
010100 (20)
010011 (19)
010010 (18)
010001 (17)
010000 (16)
001111 (15)
Typical PLL Lock Ranges
f
2056
2002
1982
1964
1947
1927
1907
1894
1872
1852
1841
1816
1796
1789
1764
1746
1738
1714
1700
1689
1657
1641
1610
1597
1568
1553
1525
1511
1484
1470
1441
1429
1403
1390
1362
1352
1325
1314
1290
1276
1253
1239
1183
1204
1151
1171
1148
1137
LOW
Typ at 25°C
Auto mode
VCO Frequency Range in MHz
f
2170
2113
2093
2075
2057
2037
2016
2003
1981
1960
1948
1923
1903
1895
1871
1853
1842
1820
1804
1790
1757
1738
1707
1689
1661
1641
1613
1595
1570
1552
1525
1509
1485
1469
1443
1429
1405
1390
1368
1351
1331
1313
1255
1275
1221
1240
1218
1204
HIGH
f
2105
2048
2029
2010
1992
1971
1951
1936
1913
1892
1881
1855
1835
1828
1803
1784
1776
1752
1737
1726
1695
1679
1649
1635
1607
1592
1562
1548
1519
1506
1474
1463
1433
1422
1391
1380
1352
1340
1315
1302
1277
1264
1205
1227
1172
1193
1170
1159
LOW
Typ over Temp
Auto mode
f
2138
2081
2061
2043
2026
2006
1986
1972
1952
1931
1920
1895
1874
1867
1844
1826
1815
1794
1779
1764
1734
1714
1684
1666
1639
1617
1592
1572
1549
1528
1504
1487
1464
1447
1423
1407
1385
1369
1350
1332
1313
1295
1240
1259
1207
1224
1204
1189
HIGH
Rev. A | Page 37 of 56
PLL Band Select
001110 (14)
001101 (13)
001100 (12)
001011 (11)
001010 (10)
001001 (9)
001000 (8)
000111 (7)
000110 (6)
000101 (5)
000100 (4)
000011 (3)
000010 (2)
000001 (1)
000000 (0)
VCO Frequency Ranges
Because the PLL band covers greater than a 2× frequency range,
there can be two options for the PLL band select: one at the low
end of the range and one at the high end of the range. Under
these conditions, the VCO phase noise is optimal when the user
selects the band select value corresponding to the high end of the
frequency range. Figure 75 shows how the VCO bandwidth and
the optimal VCO frequency varies with the band select value.
VCO Frequency Ranges over Temperature
The specifications given over temperature in Table 18 are for a
single part in a single lot. Part-to-part, and lot-to-lot, these
specifications can exhibit a mean shift of several register
settings. Systems should be designed to take this potential shift
into account to maintain optimal PLL performance.
PLL Loop Filter Bandwidth
The loop filter bandwidth of the PLL is programmed via SPI
Register 0x0A, Bits<4:0>. Changing these values switches
capacitors on the internal loop filter. No external loop filter
components are required. This loop filter has a pole at 0 (P1),
and then a zero (Z1) pole (P2) combination. Z1 and P2 occur
within a decade of each other. The location of the zero pole is
determined by Bits<4:0>. For a setting of 00000, the zero pole
occurs near 10 MHz. By setting Bits<4:0> to 11111, the Z1/P2
combination can be lowered to approximately 1 MHz. The
relationship between Bits<4:0> and the position of the zero pole
between 1 MHz and 10 MHz is linear. The internal components
are not low tolerance, however, and can drift by as much as ±30%.
For optimal performance, the bandwidth adjustment
(Register 0x0A, Bits<4:0>) should be set to 11111 for all
operating modes with PLL enabled. The PLL bias settings
Typical PLL Lock Ranges
f
1116
1106
1086
1075
1055
1045
1027
1016
998
987
960
933
908
883
859
LOW
AD9776/AD9778/AD9779
Typ at 25°C
VCO Frequency Range in MHz
f
1184
1171
1152
1138
1119
1107
1090
1076
1059
1046
1017
989
962
936
911
HIGH
f
1137
1127
1106
1095
1075
1065
1047
1034
1016
1005
977
949
923
898
873
LOW
Typ over Temp
1004
f
1170
1157
1138
1124
1106
1093
1076
1062
1046
1032
976
950
925
899
HIGH

Related parts for AD9778