AD9778 Analog Devices, AD9778 Datasheet - Page 35

• Manufacturer Part Number: AD9778
• Description: Dual 14-Bit, 1 GSPS, Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9778

• Resolution (bits): 14bit
• Dac Update Rate: 1GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

INTERPOLATION FILTER MINIMUM AND
MAXIMUM BANDWIDTH SPECIFICATIONS
The AD977x uses a novel interpolation filter architecture that
allows DAC IF frequencies to be generated anywhere in the
spectrum. Figure 68 shows the traditional choice of DAC IF
output bandwidth placement. Note that there are no possible
filter modes in which the carrier can be placed near 0.5 × f
1.5 × f
The filter architecture not only allows the interpolation filter
pass bands to be centered in the middle of the input Nyquist
zones (as explained in this section), but also allows the possi-
bility of a 3 × f
combinations, a carrier of given bandwidth can be placed
anywhere in the spectrum and fall into a possible pass band of
the interpolation filters. The possible bandwidths accessible
with the filter architecture are shown in Figure 69 and
Figure 70. Note that the shifted and nonshifted filter modes
are all accessible by programming the filter mode for the
particular interpolation rate.
Figure 69. Nonshifted Bandwidths Accessible with the Filter Architecture
Figure 68. Traditional Bandwidth Options for TxDAC Output IF
DATA
–10
–20
–30
–40
–50
–60
–70
–80
–10
–20
–30
–40
–50
–60
–70
–80
10
10
0
0
–4
–4
, 2.5 × f
DAC
–3
–3
DATA
/8 modulation mode. With all of these filter
, and so on.
–2
–2
ASSUMING 8× INTERPOLATION
ASSUMING 8× INTERPOLATION
f
f
OUT
OUT
–1
–1
(× Input Data Rate),
(× Input Data Rate),
0
0
1
1
2
2
3
3
4
4
DATA
Rev. A | Page 35 of 56
,
With this filter architecture, a signal placed anywhere in the
spectrum is possible. However, the signal bandwidth is limited
by the input sample rate of the DAC and the specific placement
of the carrier in the spectrum. The bandwidth restriction
resulting from the combination of filter response and input
sample rate is often referred to as the synthesis bandwidth, since
this is the largest bandwidth that the DAC can synthesize.
The maximum bandwidth condition exists if the carrier is
placed directly in the center of one of the filter pass bands. In
this case, the total 0.1 dB bandwidth of the interpolation filters
is equal to 0.8 × f
width as a fraction of DAC output sample rate drops by a factor
of 2 for every doubling of interpolation rate. The minimum
bandwidth condition exists, for example, if a carrier is placed at
0.25 × f
enabled, the high end of the filter response cuts off at 0.4 × f
thus limiting the high end of the signal bandwidth. If the shifted
filter response is enabled instead, then the low end of the filter
response cuts off at 0.1 × f
signal bandwidth. The minimum bandwidth specification that
applies for a carrier at 0.25 × f
minimum bandwidth behavior is repeated over the spectrum
for carriers placed at (±n ± 0.25) × f
DRIVING THE REFCLK INPUT
The REFCLK input requires a low jitter differential drive signal.
It is a PMOS input differential pair powered from
the 1.8 V supply, therefore, it is important to maintain the
specified 400 mV input common-mode voltage. Each input
pin can safely swing from 200 mV p-p to 1 V p-p about the
400 mV common-mode voltage. While these input levels are
not directly LVDS-compatible, REFCLK can be driven by an
offset ac-coupled LVDS signal, as shown in Figure 71.
Figure 70. Shifted Bandwidths Accessible with the Filter Architecture
–10
–20
–30
–40
–50
–60
–70
–80
DATA
10
0
–4
. In this situation, if the nonshifted filter response is
–3
DATA
. As Table 17 shows, the synthesis band-
–2
ASSUMING 8 × INTERPOLATION
AD9776/AD9778/AD9779
f
OUT
DATA
–1
( × Input Data Rate),
, thus limiting the low end of the
DATA
0
is therefore 0.3 × f
DATA
, where n is any integer.
1
2
3
DATA
. The
4
DATA
,